參數(shù)資料
型號(hào)： ST52X420
廠商： 意法半導(dǎo)體
元件分類(lèi)： ADC
英文描述： 8-BIT INTELLIGENT CONTROLLER UNIT (ICU) Three Timer/PWMs, ADC, WDG
中文描述： 8位智能控制器病房（ICU）3個(gè)定時(shí)器/的PWM，ADC的，水分散粒劑
文件頁(yè)數(shù)： 47/84頁(yè)
文件大?。?/td> 1274K
代理商： ST52X420
ST52T410/ST52T420/E420
47/84
8 A/D CONVERTER (ST52X420 ONLY)
8.1 Introduction
The A/D Converter of ST52x420 is an 8-bit analog
to digital converter with up to 8 analog inputs
offering 8 bit resolution with a total accuracy of 1
LSB and a typical conversion time of 8.2
μ
s with a
20 MHz clock. This period also includes the 5.1
μ
s
of the integral Sample and Hold circuitry, which
minimizes the need for external components and
allows quick sampling of the signal for a minimum
warping effect and Integral conversion error.
Conversion is performed in 82 A/D clock
pulses.
The A/D clock is derived from the clock master.
The maximum A/D clock frequency has to be 10
MHz. When the master clock is higher than 10
MHz it has to be divided by 2 using the SCK bit of
the A/D configuration register REG_CONF 3 (See
Table 8.1).
The A/D peripheral converts the input voltage with
a process of successive approximations using a
fixed clock frequency derived from the oscillator.
The conversion range is between the analog
V
SS
and V
DD
references.
The converter uses a fully differential analog input
configuration for the best noise immunity and
Figure 8.1 A/D Converter Structure
precision performance, along with one separate
supply (V
DDA
), allowing the best supply noise
rejection.
Up to 8 multiplexed Analog Inputs are available. A
group of signals can be converted sequentially by
simply programming the starting address of the
last analog channel to be converted.
Single or continuous conversion mode are
available.
The result of the conversion is stored in an 8-bit
Input Register (from IR 1 to IR 8).
The A/D converter is controlled via the
Configuration Register REG_CONF 3.
A Power-Down programmable bit allows the A/D
converter to be set to a minimum consumption idle
status.
The ST52x420 Interrupt Unit provides one
maskable channel for the End of Conversion
(EOC).
8.2 Operational Description
The conversion is monotonic, meaning that the
result never decreases if the analog input doesn
’
t
and never increases if the analog input doesn
’
t.
If input voltage is greater than or equal to V
dda
(Voltage Reference high) then the result is equal to
FFh (full scale) without an overflow indication.
PB0/AIN0
PB1/AIN1
PB2/AIN2
PB3/AIN3
PB7/PA7/AIN7
PB6/AIN6
PB5/AIN5
PB4/AIN4
ANALOG
MUX
SUCCESSIVE APPROXMATION
A/D CONVERTER
A/D CHANNEL 7
A/D CHANNEL 6
A/D CHANNEL 5
A/D CHANNEL 4
A/D CHANNEL 3
A/D CHANNEL 2
A/D CHANNEL 1
A/D CHANNEL 0
INPUT REGISTER
1 ÷ 8
SAMPLE
&
HOLD
CH2
CH1
CH0
SCK
SEQ
POW
LP
STR
CONFIGURATION REGISTER 3
CONTROL
LOGIC
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