參數(shù)資料
型號: ST52X420
廠商: 意法半導體
元件分類: ADC
英文描述: 8-BIT INTELLIGENT CONTROLLER UNIT (ICU) Three Timer/PWMs, ADC, WDG
中文描述: 8位智能控制器病房(ICU)3個定時器/的PWM,ADC的,水分散粒劑
文件頁數(shù): 35/84頁
文件大?。?/td> 1274K
代理商: ST52X420
ST52T410/ST52T420/E420
35/84
and the watchdog remain active. During WAIT
mode, Interrupts are enabled. The MCU will
remain in Wait mode until an Interrupt or a RESET
occurs, whereupon the Program Counter jumps to
the interrupt service routine or, if a RESET occurs,
at the beginning of the user program.
REMARK:
In Wait mode the CPU clock does not
stop.
5.3.2 Halt Mode
Halt mode is MCU
s lowest power consumption
mode, which is entered by executing the HALT
instruction. The internal oscillator is turned off,
causing all internal processing to stop, including
the operations of the on-chip peripherals.
Figure 5.2 Reset Block Diagram
Figure 5.3 Simple Reset Circuit
Halt mode cannot be used when the watchdog
is enabled.
If the HALT instruction is executed while the
watchdog system is enabled, it will be skipped
without modifying the normal CPU operations.
The ICU can exit Halt mode after an external inter-
rupt or reset. The oscillator is then turned on and
stabilization time is provided before restarting
CPU operations. Stabilization time is 4096 CPU
clock cycles after the interrupt and 1.000.000 after
the Reset.
After the start up delay, the CPU restarts opera-
tions by serving the external interrupt routine.
Reset makes the ICU exit from HALT mode and
restart, after the delay, from the beginning of the
user program after the delay.
Warning
: if the External Interrupt is disabled, the
ICU exits from the Halt mode and jumps
to the
lower priority interrupt routine.
Figure 5.4 WAIT Flow Chart
WATCHDOG RESET
RESET
INTERNAL
RESET
Vcc
100 F
10k
2.2k
2.2k
1 F
RESET
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