參數(shù)資料
型號: ST52X420
廠商: 意法半導(dǎo)體
元件分類: ADC
英文描述: 8-BIT INTELLIGENT CONTROLLER UNIT (ICU) Three Timer/PWMs, ADC, WDG
中文描述: 8位智能控制器病房(ICU)3個定時器/的PWM,ADC的,水分散粒劑
文件頁數(shù): 40/84頁
文件大?。?/td> 1274K
代理商: ST52X420
ST52T410/T420/E420
40/84
Example 1
:
IF Input
1
IS NOT Mbf
1
AND Input
4
is Mbf
12
OR Input
3
IS Mbf
8
THEN Crisp
1
is codified by the following instructions:
Example 2
, the priority of the operator is fixed by the brackets:
IF (Input
3
IS Mbf
1
AND Input
4
IS NOT Mbf
15
) OR (Input
1
IS Mbf
6
OR Input
6
IS NOT Mbf
14
) THEN Crisp
2
At the end of the fuzzy rule, by using the instruction
OUT
RAM_reg
, a byte is written. Afterwards, the
control of the algorithm returns to the CU.
LDN 1 1
calculates the NOT
α
value of Input
1
with Mbf
1
and stores the result in internal registers
LDP 4 12
fixes the
α
value of Input
4
with Mbf
12
and stores the result in internal registers
FZAND
implements the operation AND between the results obtained with the previous instructions
LDK
stores the result of the previous operation in internal DPU registers
LDP 3 8
fixes the
α
value of Input
3
with Mbf
8
and stores the result in internal registers
FZOR
implements the operation OR between the results obtained with the previous instructions
CON
crisp
1
multiplies the result of the last
operation with the crisp value
crisp
1
LDP 3 1
fixes the
α
value of Input
3
with Mbf
1
and stores the result in internal registers
LDN 4 15
calculates the NOT
α
value of Input
4
with Mbf
15
and stores the result in internal registers
FZAND
implements the operation AND between the results obtained with the previous instructions
SKM
stores the result of the previous operation in register M
LDP 1 6
fixes the
α
value of Input
1
with Mbf
6
and stores the result in internal registers
LDN 2 14
calculates the NOT
α
value of Input
6
with Mbf
14
and stores the result in internal registers
FZOR
implements the operation OR between the results obtained with the previous instructions
LDK
stores the result of the previous operation in internal DPU registers
LDM
copies the value of the register M in internal DPU registers
FZOR
implements the operation OR between the last two values stored in DPU registers
CON
crisp
2
multiplies the result of the last
operation with the crisp value
crisp
2
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