參數(shù)資料
型號(hào): ST52X420
廠商: 意法半導(dǎo)體
元件分類: ADC
英文描述: 8-BIT INTELLIGENT CONTROLLER UNIT (ICU) Three Timer/PWMs, ADC, WDG
中文描述: 8位智能控制器病房(ICU)3個(gè)定時(shí)器/的PWM,ADC的,水分散粒劑
文件頁(yè)數(shù): 18/84頁(yè)
文件大小: 1274K
代理商: ST52X420
ST52T410/ST52T420/E420
18/84
The STACK POINTER indicates the first level
available to store data. When a subroutine call or
interrupt request occurs, the content of the PC and
the current set of flags are stored into the level
located by the STACK POINTER.
When a interrupt return occurs (RETI instruction),
the data stored in the highest stack level is
restored back into the PC and current flags.
Instead, when a subroutine return occurs (RET
instruction) the data stored in the highest stack
level are restored in the PC not affecting the flags.
These operating modes are illustrated in Figure
2.4.
Note:
The user must pay close attention to avoid
overwriting RAM locations where the STACK could
be stored
.
2.3.2 Input Registers Bench.
The Input Registers (IR) bench consists of 18 8-bit
registers containing data or the status of the
peripherals.
All the registers can be specified by using a
decimal address (for example, 0 identifies the first
register of the IR).
The assembler instruction:
LDRI RAM_Reg. IR_i
loads the value of the i-th IR in the RAM location
identified by the
RAM_Reg
address.
The first input register is dedicated to store the
value of the stack pointer. The next 8 registers
(ADC_OUT_0:7) of the IR are dedicated to the 8
converted values
deriving from
(ST52x420 only). The last 9 Input Registers
contain data from the I/O ports and PWM/Timers.
The following table summarizes the IR address
and the relative peripherals. In order to simplify the
concept, a mnemonic name is assigned to the
registers.
The
same
VISUALSTUDIO
development tools
the
ADC
name
is
used
in
Figure 2.4 Stack Operation
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