參數(shù)資料
型號(hào)： ST52X420
廠商： 意法半導(dǎo)體
元件分類： ADC
英文描述： 8-BIT INTELLIGENT CONTROLLER UNIT (ICU) Three Timer/PWMs, ADC, WDG
中文描述： 8位智能控制器病房（ICU）3個(gè)定時(shí)器/的PWM，ADC的，水分散粒劑
文件頁(yè)數(shù)： 50/84頁(yè)
文件大?。?/td> 1274K
代理商： ST52X420
ST52T410/ST52T420/E420
50/84
9 WATCHDOG TIMER
9.1 Operational Description
The Watchdog Timer (WDT) is used to detect the
occurrence of a software fault, usually generated
by external interference or by unforeseen logical
conditions, which cause the application program to
abandon its normal sequence. The WDT circuit
generates an MCU reset on expiry of a
programmed time period, unless the program
refreshes the WDT before the end of the
programmed time delay.
16 different delays can be selected by using the
WDT configuration register.
After the end of the delay programmed by the
configuration register if the WDT is activated (by
using the assembler instruction WDTSFR), it starts
a reset cycle pulling the reset pin low.
Once the WDT has been activated the application
program has to refresh this peripheral (by the
WDTSFR
instruction) at regular intervals during
normal operation in order to prevent an MCU reset.
In order to stop the WDT during user program
execution the instruction
WDTSLP
has to be used.
Figure 9.1 Watchdog Block Diagram
The working frequency of the WDT (PRES CLK in
the Figure 9.1) is equal to the clock master. The
clock master is divided by 500, obtaining the WDT
CLK signal, which is used to fix the timeout of the
WDT.
According to the WDT configuration register
values, a WDT delay may be defined between 0.1
ms and 937.5 mS when the clock master is 5 MHz.
By changing the clock master frequency the
timeout delay can be calculated according to the
configuration register values REG_CONF 2, as
described in the following section.
Warning:
changing the REG_CONF2 value when
the WDT is active, a WDT reset is generated and
the CPU is restarted. To avoid this side effect, use
the
WDTSLP
instruction before changing the
REG_CONF2.
Table 9.1 Watchdog Timing range (CLK=5
MHz)
WDT timeout period (ms)
min
0.1
max
937.5
D0
D1
D2
D3
REG_CONF 2
RESET
WDTRFR
PRES CLK = CLK MASTER
WDTSLP
PRESCALER
WDT
RESET
GENERATOR
RESET
WTD CLK
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