參數(shù)資料
型號(hào)： SPAK56F826BU80
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： 16-BIT, 80 MHz, OTHER DSP, PQFP100
封裝： LQFP-100
文件頁(yè)數(shù)： 8/53頁(yè)
文件大小： 829K
代理商： SPAK56F826BU80
16
DSP56F826 Preliminary Technical Data
MOTOROLA
Part 3 Specifications
3.1 General Characteristics
The DSP56F826 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs.
The term 5-volt tolerant refers to the capability of an I/O pin, built on a 3.3V compatible process technology,
to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V- compatible
I/O voltage levels. A standard 3.3V I/O is designed to receive a maximum voltage of 3.3V
± 10% during
normal operation without causing damage. This 5V tolerant capability, therefore, offers the power savings
of 3.3V I/O levels while being able to receive 5V levels without being damaged.
Absolute maximum ratings given in Table 4 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.
The DSP56F826 DC/AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However,
normal
precautions
are
advised
to
avoid
application of any voltages higher than maximum rated
voltages
to this
high-impedance circuit. Reliability
of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.
Table 4. Absolute Maximum Ratings
Characteristic
Symbol
Min
Max
Unit
Supply voltage, core
VDD
1
1.
VDD must not exceed VDDIO
VSS – 0.3
VSS + 3.0
V
Supply voltage, IO
Supply voltage, Analog
VDDIO
2
VDDA
2
2.
VDDIO and VDDA must not differ by more that 0.5V
VSSIO – 0.3
VSSA – 0.3
VSSIO + 4.0
VSSA + 4.0
V
Digital input voltages
Analog input voltages - XTAL, EXTAL
VIN
VINA
VSSIO – 0.3
VSSA – 0.3
VSSIO + 5.5
VSSA + 3.0
V
Current drain per pin excluding VDD, VSS, VDDA, VSSA,
VDDIO, VSSIO
I
—
10
mA
Junction temperature
TJ
—
150
°C
Storage temperature range
TSTG
–
55
150
°C
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