參數(shù)資料
型號(hào)： SPAK56F826BU80
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 16-BIT, 80 MHz, OTHER DSP, PQFP100
封裝： LQFP-100
文件頁(yè)數(shù)： 23/53頁(yè)
文件大小： 829K
代理商： SPAK56F826BU80
DSP56F826 Description
MOTOROLA
DSP56F826 Preliminary Technical Data
3
Sixteen (16) dedicated general purpose I/O (GPIO) pins
Thirty (30) shared general purpose I/O (GPIO) pins
Computer-Operating Properly (COP) Watchdog timer
Two external interrupt pins
External reset pin for hardware reset
JTAG/On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent debugging
Software-programmable, Phase Lock Loop-based frequency synthesizer for the DSP core clock
Fabricated in high-density EMOS with 5V tolerant, TTL-compatible digital inputs
One Time of Day module
1.1.4
Energy Information
Dual power supply, 3.3V and 2.5V
Wait and Multiple Stop modes available
1.2 DSP56F826 Description
The DSP56F826 is a member of the DSP56800 core-based family of Digital Signal Processors (DSPs). It
combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with
a flexible set of peripherals to create an extremely cost-effective solution for general purpose applications.
Because of its low cost, configuration flexibility, and compact program code, the DSP56F826 is well-
suited for many applications. The DSP56F826 includes many peripherals that are especially useful for
applications such as: noise suppression, ID tag readers, sonic/subsonic detectors, security access devices,
remote metering, sonic alarms, POS terminals, feature phones.
The DSP56800 core is based on a Harvard-style architecture consisting of three execution units operating
in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C/C++ Compilers to enable rapid
development of optimized control applications.
The DSP56F826 supports program execution from either internal or external memories. Two data operands
can be accessed from the on-chip Data RAM per instruction cycle. The DSP56F826 also provides two
external dedicated interrupt lines, and up to 46 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The DSP56F826 DSP controller includes 31.5K words (16-bit) of Program Flash and 2K words of Data
Flash (each programmable through the JTAG port) with 512 words of Program RAM, and 4K words of Data
RAM. It also supports program execution from external memory.
The DSP56F826 incorporates a total of 2K words of BootFLASH for easy customer-inclusion of field-
programmable software routines that can be used to program the main Program and Data Flash memory
areas. Both Program and Data Flash memories can be independently bulk-erased or erased in page sizes of
256 words. The BootFLASH memory can also be either bulk- or page-erased.
This DSP controller also provides a full set of standard programmable peripherals including one
Synchronous Serial Interface (SSI), one Serial Peripheral Interface (SPI), the option to select a second SPI
or two Serial Communications Interfaces (SCIs), and one Quad Timer. The SSI, SPI, and quad timer can be
used as General Purpose Input/Outputs (GPIOs) if a timer function is not required.
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