參數(shù)資料
型號: SDED5-008G-NCY
廠商: SANDISK CORP
元件分類: 存儲(chǔ)控制器/管理單元
英文描述: FLASH MEMORY DRIVE CONTROLLER, PBGA115
封裝: 12 X 18 MM, 1.40 MM HEIGHT, FBGA-115
文件頁數(shù): 36/87頁
文件大?。?/td> 1675K
代理商: SDED5-008G-NCY
Rev. 1.2
mDOC H3 Registers
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
41
92-DS-1205-10
7.3
Registers Description
This section describes various mDOC H3 registers and their functions.
7.3.1
Paged RAM Command Register
Description:
This 8-bit register is used to enable Write to other Paged RAM registers.
Address (hex): 0030 (both 8KB window and 128KB Window)
Type:
Write
D7
D6
D5
D4
D3
D2
D1
D0
Read/Write
W
Bit Name
COMMAND
Reset Value
N/A
Bit No.
Description
COMMAND
COMMAND The value 71H must be written to enable a subsequent write cycle to the
Paged RAM Page Select register. All other values: Reserved.
7.3.2
Paged RAM Select Register
Description:
This 8-bit register is used to initiate a download operation of the specified 1KB
page. If the value 71H is not written to the Paged RAM Command register
immediately before writing this register, the write cycle will be ignored.
Address (hex): 0070 (both 8KB window and 128KB Window)
Type:
Write
D7
D6
D5
D4
D3
D2
D1
D0
Read/Write
W
Description
SEQ
PAGE
Reset Value
N/A
00H
Bit No.
Description
SEQ
Sequential indication. Setting this bit initiates a download from the NEXT_PAGE pointer
of the previously downloaded page. The value written to the PAGE field is ignored.
PAGE
Only significant when writing a 0 to the SEQ field. Only value 00H is supported.
PAGE value of 00H loads the same data as in hardware or software reset.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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