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參數(shù)資料
| 型號： | SDED5-008G-NCY |
| 廠商： | SANDISK CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | FLASH MEMORY DRIVE CONTROLLER, PBGA115 |
| 封裝： | 12 X 18 MM, 1.40 MM HEIGHT, FBGA-115 |
| 文件頁數(shù)： | 23/87頁 |
| 文件大?。?/td> | 1675K |
| 代理商： | SDED5-008G-NCY |
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Rev. 1.2
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
3
92-DS-1205-10
mDOC H3 8Gb/16Gb/32Gb/64Gb
- 115-ball Fine-Pitch Ball Grid
Array (FBGA) 12x18mm
Ball to ball compatible with
mDOC G3/G4/H1 families.
Enhanced performance by implementation
of:
Multi-plane operations
DMA support
Burst operation
Dual Data RAM buffering
Read/Write Cache
Fast partition configuration
Powerful data integrity with a robust Error
Detection Code/Error Correction Code
(EDC/ECC) specifically tailored for the most
advanced flash technology.
Strong flash endurance with TrueFFS
advanced flash management software.
Reduced complexity for the host system by
moving flash management functionality to
the device.
Plug & Play integration with the host
system, due to embedding TrueFFS within
the device itself.
Support for major mobile operating
systems (OSs), including Symbian OS,
Windows Mobile, Windows CE, Linux and
more.
Compatibility with major mobile CPUs
Performance:
Sustained write: 4-8 MB/sec.
Sustained read: 15-25 MB/sec
PROTECTION & SECURITY-
ENABLING
16-byte Unique Identification (UID)
number.
14 configurable protected partitions for
data and code:
Write protected
Read and Write protected
One Time Programmable (OTP)
Protection key and LOCK# signal
Sticky Lock (SLOCK) to lock boot
partition
Protected Bad Block Table.
RELIABILITY AND DATA INTEGRITY
Hardware on-the-fly Error Detection
Code/Error Correction Code (EDC/ECC),
based on a BCH algorithm, tailored for the
most advanced flash technology.
Data integrity after power failure.
Transparent bad-block management.
Dynamic and static wear-leveling.
BOOT CAPABILITY
32KB Programmable Boot Block with XIP
capability to replace boot ROM or NOR.
254KB Paged RAM IPL
Boot Agent for automatic download of
boot code to the Programmable Boot
Block.
Asynchronous Boot mode to enable ARM-
based CPUs, e.g. TI OMAP, Intel PXAxxx,
to boot without the need for external glue
logic.
Exceptional boot performance with Burst
operation and DMA support enhanced by
external clock.
HARDWARE COMPATIBILITY
Configurable interface: simple SRAM-like
or multiplexed address/data interface.
CPU compatibility, including:
ARM-based CPUs
Texas Instruments OMAP, DBB
Marvell PXAxxx family
Infineon xGold family
Analog Devices (ADI) digital
Baseband devices
Freescale i.MXxx Application
processors and i.xx digital
Baseband devices
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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| SDED5-512M-N9Y | 功能描述:IC MDOC H3 4GB 115-FBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:150 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-DFN（2x3） 包裝:管件 產(chǎn)品目錄頁面:1445 (CN2011-ZH PDF) |
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