參數(shù)資料
型號： S71PL191HB0BFI100
廠商： SPANSION LLC
元件分類： 存儲器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA73
封裝： 9 X 13 MM, LEAD FREE, FBGA-73
文件頁數(shù)： 91/172頁
文件大?。?/td> 4662K
代理商： S71PL191HB0BFI100
May 7, 2004 S29PL127H_129H_00A1
S29PL127H/S29PL129H
9
Pre l i m i n a r y
DEVICE BUS OPERATIONS
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to
the internal state machine. The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the inputs and control levels they
require, and the resulting output. The following subsections describe each of
these operations in further detail.
Table 1. S29PL127H/S29PL129H Device Bus Operations
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 8.5–9.5 V, X = Don’t Care, SA = Sector
Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. The sector protect and sector unprotect functions may also be implemented via programming equipment.
2. WP#/ACC must be high when writing to sectors 0, 1, 268, or 269. (S29PL127H); or SA1-133, SA1-134, SA2-0,
or SA2-1 (S29PL129H).
3. For S29PL129H, CE1# and CE2# must not be Low simultaneously.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the OE# and appro-
priate CE# pins to VIL. CE# is the power control. OE# is the output control and
gates array data to the output pins. WE# should remain at VIH.
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data on the device data
outputs. Each bank remains enabled for read access until the command register
contents are altered.
Refer to the AC Characteristics table for timing specifications and to Figure 11 for
the timing diagram. ICC1 in the DC Characteristics table represents the active cur-
rent specification for reading array data.
Random Read (Non-Page Read)
Address access time (tACC) is equal to the delay from stable addresses to valid
output data. The chip enable access time (tCE) is the delay from the stable ad-
dresses and stable CE# to valid data at the output inputs. The output enable
Operation
CE#
(Note 3)
OE#
WE#
RESET#
WP#/ACC
Addresses
(Amax–A0)
DQ15–
DQ0
Read
L
H
X
AIN
DOUT
Write
L
H
L
H
X
AIN
DIN
Standby
VIO±
0.3 V
X
VIO ±
0.3 V
X (Note 2)
X
High-Z
Output Disable
L
H
X
High-Z
Reset
X
L
X
High-Z
Temporary Sector Unprotect (High
Voltage)
X
VID
X
AIN
DIN
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