參數(shù)資料
型號： S71PL191HB0BFI100
廠商： SPANSION LLC
元件分類： 存儲器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA73
封裝： 9 X 13 MM, LEAD FREE, FBGA-73
文件頁數(shù)： 67/172頁
文件大?。?/td> 4662K
代理商： S71PL191HB0BFI100
64
32 Mb pSRAM (Supplier 2)
S71PL191_193Hx0_00A1 March 10, 2004
Adva nce
Inform at i o n
AC Characteristics (VCC=2.7~3.1V, TA=-40 to 85°C)
1. tWP(min)=70ns for continuous write operation over 50 times.
Timing Diagrams
Parameter List
Symbol
Speed Bins
Units
70ns
Min
Max
Read
Read Cycle Time
tRC
70
-
ns
Address Access Time
tAA
-
70
ns
Chip Select to Output
tCO
-
70
ns
Output Enable to Valid Output
tOE
-
35
ns
UB#, LB# Access Time
tBA
-
70
ns
Chip Select to Low-Z Output
tLZ
10
-
ns
UB#, LB# Enable to Low-Z Output
tBLZ
10
-
ns
Output Enable to Low-Z Output
tOLZ
5
-
ns
Chip Disable to High-Z Output
tHZ
0
25
ns
UB#, LB# Disable to High-Z Output
tBHZ
0
25
ns
Output Disable to High-Z Output
tOHZ
0
25
ns
Output Hold from Address Change
tOH
5
-
ns
Write
Write Cycle Time
tWC
70
-
ns
Chip Select to End of Write
tCW
60
-
ns
Address Set-up Time
tAS
0
-
ns
Address Valid to End of Write
tAW
60
-
ns
UB#, LB# Valid to End of Write
tBW
60
-
ns
Write Pulse Width
tWP
55 (note 1)
-
ns
Write Recovery Time
tWR
0
-
ns
Write to Output High-Z
tWHZ
0
25
ns
Data to Write Time Overlap
tDW
30
-
ns
Data Hold from Write Time
tDH
0
-
ns
End Write to Output Low-Z
tOW
5
-
ns
Figure 30. Timing Waveform of Read Cycle(Note 1)(Address Controlled,
CS#=OE#=VIL, ZZ#=WE#=VIH, UB# or/and LB#=VIL)
Address
Data Out
Previous Data Valid
Data Valid
tAA
tRC
tOH
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