
May 7, 2004 S29PL127H_129H_00A1
S29PL127H/S29PL129H
3
Pre l i m i n a r y
Device programming occurs by executing the program command sequence. The
Unlock Bypass mode facilitates faster programming times by requiring only two
write cycles to program data instead of four. Device erasure occurs by execut-
ing the erase command sequence.
The host system can detect whether a program or erase operation is complete
by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a pro-
gram or erase cycle has been completed, the device is ready to read array data
or accept another command.
The sector erase architecture allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is
fully erased when shipped from the factory.
Hardware data protection measures include a low VCC detector that auto-
matically inhibits write operations during power transitions. The hardware sec-
tor protection feature disables both program and erase operations in any
combination of sectors of memory. This can be achieved in-system or via pro-
gramming equipment.
The Erase Suspend/Erase Resume feature enables the user to put erase on
hold for any period of time to read data from, or program data to, any sector
that is not selected for erasure. True background erase can thus be achieved. If
a read is needed from the SecSi Sector area (One Time Program area) after an
erase suspend, then the user must use the proper command sequence to enter
and exit this region.
The device offers two power-saving features. When addresses have been stable
for a specified amount of time, the device enters the automatic sleep mode.
The system can also place the device into the standby mode. Power consump-
tion is greatly reduced in both these modes.
The device electrically erases all bits within a sector simultaneously via Fowler-
Nordheim tunneling. The data is programmed using hot electron injection.