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參數(shù)資料
| 型號： | S71PL191HB0BFI100 |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA73 |
| 封裝： | 9 X 13 MM, LEAD FREE, FBGA-73 |
| 文件頁數(shù)： | 41/172頁 |
| 文件大?。?/td> | 4662K |
| 代理商： | S71PL191HB0BFI100 |
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May 7, 2004 S29JL064HA1
S29JL064H
39
Pre l i m i n a r y
DQ2 toggles when the system reads at addresses within those sectors that have
been selected for erasure. (The system may use either OE# or CE# to control the
read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or
is erase-suspended. DQ6, by comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected
for erasure. Thus, both status bits are required for sector and mode information.
Refer to Table 8 to compare outputs for DQ2 and DQ6.
7 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle
shows the toggle bit timing diagram. 24 shows the differences between DQ2 and
DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to 7 for the following discussion. Whenever the system initially begins read-
ing toggle bit status, it must read DQ15–DQ0 (or DQ7–DQ0 for x8-only device)
at least twice in a row to determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit after the first read. After
the second read, the system would compare the new value of the toggle bit with
the first. If the toggle bit is not toggling, the device has completed the program
or erase operation. The system can read array data on DQ15–DQ0 (or DQ7–DQ0
for x8-only device) on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle
bit is still toggling, the system also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer toggling, the device has suc-
cessfully completed the program or erase operation. If it is still toggling, the
device did not completed the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit
is toggling and DQ5 has not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as de-
scribed in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algo-
rithm when it returns to determine the status of the operation (top of 7).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified in-
ternal pulse count limit. Under these conditions DQ5 produces a “1,” indicating
that the program or erase cycle was not successfully completed.
The device may output a “1” on DQ5 if the system tries to program a “1” to a
location that was previously programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the device halts the opera-
tion, and when the timing limit has been exceeded, DQ5 produces a “1.”
Under both these conditions, the system must write the reset command to return
to the read mode (or to the erase-suspend-read mode if a bank was previously
in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to de-
termine whether or not erasure has begun. (The sector erase timer does not
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