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參數(shù)資料
| 型號： | S3P1860-DK |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDIP20 |
| 封裝： | 0.300 INCH, DIP-20 |
| 文件頁數(shù)： | 9/95頁 |
| 文件大?。?/td> | 339K |
| 代理商： | S3P1860-DK |
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S3C1860
3-16
RESET
All reset operations are internal in the S3C1860. It has three kinds of reset sources as follows (To obtain more
information about reset operation, see Chapter 6. Remote Control Tx) :
Oscillation Start and Reset (OSR)
Reset by Halt mode release
Auto-Reset
Oscillation Start and Reset (OSR)
A system reset pulse occurs when the chip is in non-operating voltage with oscillation.
Auto-Reset
Auto-Reset circuit resets the chip every 131,072 oscillator clock cycles (288ms at a fxx = 455 kHz clock
frequency). The auto-reset counter is cleared by the rising edge of a internal P2.0 pin, by HALT, or by OSR.
Therefore, no clocks are sent to the counter and the time-out is suspended in HALT mode.
When a reset occurs during program execution, a transient condition occurs. The PA register is immediately
initialized to 0FH. The PC, however, is not reset to 0H until one instruction cycle later. For example, if PC is 1AH
when a reset pulse is generated, the instruction at 0F1AH is executed, followed by the instruction at 0F00H.
After a reset, approximately 13 msec is needed before program execution proceeds (assuming fxx = 455 kHz
ceramic oscillation).
Upon initialization, registers are set as follows:
PC register to 0 in next instruction cycle
PA and PB registers to 0FH (15th page)
SF and SL registers to 1
H,L registers to unknown state
All internal/external output pins (P3.0-P3.3, P2.1-P2.4, P2.9, P2.10, P2.12 and P2.13 except P2.0/REM) to
low.
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