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| 型號： | S3P1860-DK |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDIP20 |
| 封裝： | 0.300 INCH, DIP-20 |
| 文件頁數(shù)： | 5/95頁 |
| 文件大?。?/td> | 339K |
| 代理商： | S3P1860-DK |
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S3C1860
3-12
Arithmetic Logic Unit (ALU), Accumulator (A)
The SMCS-51 CPU contains an ALU and its own 4-bit register (accumulator) which is the source and destination
register for most I/O, arithmetic, logic, and data memory access operations. Arithmetic functions and logical
operations will set the status flag (SF) to "0" or "1".
Status Latch (SL)
The Status latch (SL) flag is a 1-bit flip-flop register. Only the "CPNE L,A" instruction can change the value of SL.
If the result of a "CPNE L,A" instruction is true, the SL is set to "1"; If not true, to "0".
Status Flag : SF
The Status Flag (SF) is a 1-bit flip-flop register which enables programs to conditionally skip an instruction. All
instructions, including JP and CALL, are executed when SF is "1".
But if SF is "0", the program executes NOP instruction instead of JP or CALL and resets SF to "1". Then,
program execution proceeds. The following instructions set the SF to "0".
Arithmetic Instructions
ADDS
A,#n
; if no carry
ADDS
A,@HL
; if no carry
INCS
A,@HL
; if no carry
INCS
A
; if no carry
INCS
L
; if no carry
SUBS
A,@HL
; if borrow
DECS
A,@HL
; if borrow
DECS
A
; f borrow
DECS
L
; if borrow
Compare Instructions
CPNE
@HL,A
; if M(H,L) = (A)
CPNZ
@HL
; if M(H,L) = 0
CPNE
L,#n
; if (L) = #n
CPNE
L,A
; if (L) = (A)
CPNE
A,@HL
; if (A) > M (H,L)
CPNZ
P0
; if (P0) = 0
CPBT
@HL.b
; if M(H,L,b)
≠ 1
Data Transfer Instructions
MOV
@HL+,A
; if no carry
MOV
@HL-,A
; if borrow
Logical Instructions
NOTI
A
; if (A)
≠ 0 after operation
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| S3P7048-QZ | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP42 |
| S3P72B9-QA | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP128 |
| S3C72B5XX-QA | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP128 |
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