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參數(shù)資料
| 型號(hào)： | S3P1860-DK |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDIP20 |
| 封裝： | 0.300 INCH, DIP-20 |
| 文件頁數(shù)： | 8/95頁 |
| 文件大小： | 339K |
| 代理商： | S3P1860-DK |
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S3C1860
3-15
HALT MODE
The HALT mode is used to reduce power consumption by stopping the clock and holding the states of all internal
operations fixed. This mode is very useful in battery-powered instruments. It also holds the controller in wait
status for external stimulus to start some event. The S3C1860 can be halted by programming the P2.12 pin high,
and by forcing P0 input pins (P0.0-P0.3) to high and P1 input pins (P1.0-P1.1) to high, concurrently (See Figure
3-15). When in HALT mode, the internal circuitry does not receive any clock signal, and all P2, P3 output pins
become low states. However, P2.0 pin becomes floating state, P2.1 pin retains their programmed values until the
device is re-started as follows:
Forcing any P0 and P1 input pins to low : system reset occurs and it continues to operate from the reset
address.
An oscillation stabilization time of 13 msec in fxx = 455 kHz crystal oscillation is needed for stability (See Figure
1-16).
P0.3-P0.0
P1.1-P1.0
VDD
4
Internal P2.12
Internal
HALT
System reset
4
Figure 3-15. Block Diagram of HALT Logic
Normal Mode
HALT mode
X'tal
13 msec (Minimum)
120
sec (Typical)
HALT
Figure 3-16. Release Timing for HALT or RESET to Normal Mode in Crystal Oscillation
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