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| 型號(hào)： | S3P1860-DK |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDIP20 |
| 封裝： | 0.300 INCH, DIP-20 |
| 文件頁(yè)數(shù)： | 22/95頁(yè) |
| 文件大?。?/td> | 339K |
| 代理商： | S3P1860-DK |
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S3C1840/C1850/C1860/P1860
INSTRUCTION SET
5-1
INSTRUCTION SET DESCRIPTION
Abbreviations and symbols table specifies internal architecture, instruction operand and operational symbols.
As mentioned before, JP and CALL instructions are executed normally only when SF is high. If SF is low, the
program executes NOP instruction instead of them and sets SF to high. And then, the program executes a next
instruction. In addition, JPL and CALL are long jump and long call instructions which consists of PAGE and
JP/CALL instructions.
Table 5-1. Abbreviations and Symbols
Symbol
Description
Symbol
Description
L
L register (4 bits)
SF
Status Flag
A
Accumulator (4 bits)
P3
P4-output
(L)
The contents of the L register
P0
P0 input (4 bits)
(A)
The contents of the accumulator
D
Any binary number
SL
Status latch (1 bit)
DST
Destination operand
PB
Page buffer register (4 bits)
C
Carry Flag
PA
Page address register (4bits)
SRC
Source operand
P2
P2-output
REG
Register
PC
Program counter
←
Transfer
SR
Stack register
+
Addition or increment by 1
H
H register
≤
Equal or less than
M
RAM addressed by H and L registers
( )
The complement of the contents
(H)
The contents of the H register
@
Indirect register address prefix
M (H,L)
The contents of the RAM addressed by H,L
#n
Constant n (immediate 3or 4-bit data)
b
Bit address of the RAM [(H,L)] addressed
by H,L
Is exchanged with
≠
Not equal to
Subtract or decrement by 1
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