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參數(shù)資料
| 型號： | S3P1860-DK |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDIP20 |
| 封裝： | 0.300 INCH, DIP-20 |
| 文件頁數(shù)： | 55/95頁 |
| 文件大?。?/td> | 339K |
| 代理商： | S3P1860-DK |
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REMOTE CONTROL TX. APPLICATION NOTE
S3C1840/C1850/C1860/P1860
7-2
Table 7-3. S3C1840/C1850/C1860 Functions
Description
Automatic reset by Halt mode
release
When Halt mode is released, the chip is reset after an oscillator stabilization
interval of 9 ms. (fxx = 455 kHz)
Output pin state retention
function
When the system enters Halt Mode,
P3.0-P3.3, P2.0, and P2.2-P2.5 go low level in 24 pins.
P3.0-P3.3, P2.0, and P2.2-P2.4 go low level in 20 pins.
But the P2.0 is floating state in S3C1850/C1860. (NOTE)
Auto-reset
With oscillation on and with no change to the IP2.0 output pin, a reset is
activated every 288 ms at fxx = 455 kHz.
Osc. Stabilization time
CPU instructions are executed after oscillation stabilization time has elapsed.
Other functions
Carrier frequency generator. Halt wake-up function.
NOTE : The S3C1850 has 24 pin package type only and S3C1860 has 20 pin package type only.
RESET
The S3C1840/C1850 has three kinds of reset operations:
— POR (Power-On Reset)
— Auto-reset
— Automatic reset by Halt release
The S3C1860 has three kinds of reset operations;
— OSR (Oscillation Start and Reset)
— Auto-reset
— Automatic reset by Halt release
Power-On Reset Circuits
7 pF
1 M
0.3 VDD
2.2 V
VDD
RESET
Reset Time
Figure 7-1. Power-On Reset Circuits
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