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參數(shù)資料
| 型號： | S3P1860-DK |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDIP20 |
| 封裝： | 0.300 INCH, DIP-20 |
| 文件頁數(shù)： | 58/95頁 |
| 文件大?。?/td> | 339K |
| 代理商： | S3P1860-DK |
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REMOTE CONTROL TX. APPLICATION NOTE
S3C1840/C1850/C1860/P1860
7-4
Automatic Reset by Halt Mode Release
This function resets the CPU by releasing Halt mode. The CPU is reset to its initial operating status and program
execution starts from the reset address.
Halt Mode and Automatic Reset by Halt Release
Halt mode is used to reduce power consumption by stopping the oscillation and holding the internal state. Halt
mode can be entered by forcing IP2.12 to high level (remaining input pins are non-active).
Before entering Halt mode, programmer should pre-set all key strobe output pins to active state even though Halt
mode causes some pins to remain active.
For the 24 pins, P3.0-P3.3, P2.0, P2.2- P2.4, and P2.5 are sent low and for 20 pins, P3.0-P3.3, P2.0, P2.2-P2.4
are sent low, but the P2.0 is floating state in S3C1850/C1860.. Forcing any key input port to active state causes
the clock oscillation logic to start system initialization.
At this time, the system is reset after the oscillation stabilization time elapses. A system reset causes program
execution to start from address 0F00H.
Normal Mode:
After a reset, the program
restarts from 0F00H after one
instruction in 0FxxH is
executed.('F' is page number
and 'xx' is the instruction
immediately following the
HALT instruction.)
Halt Release Signal
IP2.12 = 1, Non-Active Input Pin
Normal Mode
Halt
XO
Osc. Circuit
Wait Time
(3-4 ms)
Osc. Stabilization Timer Start
Osc. Stabilization Timer
(9 ms)
fxx = 455 kHz)
Figure 7-3. Reset Timing Diagram
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