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參數(shù)資料
| 型號(hào)： | S3P1860-DK |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDIP20 |
| 封裝： | 0.300 INCH, DIP-20 |
| 文件頁(yè)數(shù)： | 6/95頁(yè) |
| 文件大?。?/td> | 339K |
| 代理商： | S3P1860-DK |
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S3C1860
3-13
INPUT PORTS : P0, P1
The P0 and P1 input ports have internal pull-up 30-150 K
resistors, (See I/O circuit type A), each multiplexed to
a common bus (See Figure 3-13). If the P2.13 pin is programmed to low, then port 0 is selected as the input port.
Otherwise, if the P2.13 pin high, port 1 is selected.
Common Bus
MUX
P0.0-P0.3
4
P2.13 (Internal)
P1.0-P1.1
2
Figure 3-13. S3C1860 Input Port
OUTPUT PORTS : P2, P3
The P2 and P3 output ports can be configured as N-CH. Transistor (P2.0/REM only) and open drain (P2.1-P2.4,
P3.0-P3.3) as follows:
N-channel Transistor for I.R.LED drive : A CMOS P2.0 N-CH. Transistor with P2.0/REM and TEST
(see I/O Circuit Type B). P2.0/REM becomes floating state in halt mode.
N-channel open drain : An N-channel transistor to ground, compatible with CMOS and TTL.
(see I/O Circuit Type C and D).
P2.2-P2.4 and P3.0-P3.3 pins become low state in halt mode.
The L register specifies P2 output pins (P2.0/REM-P2.4, P2.9-P2.10, P2.12, and P2.13) individually as follows:
SETB P2.(L) : Set port 2 bits to correspond to L-register contents.
CLRB P2.(L) : Clear port 2 bits to correspond to L-register contents.
P3 output pins P3.0-P3.3 are parallel output pins.
For the S3C1860, only the 4-bit accumulator outputs its value to the P3 port by the output instruction “OUT P3,
@SL+ A” (the value of the Status Latch (SL) does not matter).
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