參數(shù)資料
型號(hào)： S3P1860-DK
元件分類(lèi)： 微控制器/微處理器
英文描述： 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDIP20
封裝： 0.300 INCH, DIP-20
文件頁(yè)數(shù)： 66/95頁(yè)
文件大小： 339K
代理商： S3P1860-DK
REMOTE CONTROL TX. APPLICATION NOTE
S3C1840/C1850/C1860/P1860
7-12
SMDS
When a breakpoint or single-step instruction is executed in area of PAGE and JP or CALL instruction, the JP or
CALL may jump to the wrong address, We therefore recommend using a JPL or CALL instruction (instead of
PAGE and JP or PAGE and CALL) to avoid this problems. Note that JP and CALL are 2-byte instructions.
Programming Guidelines for Reset Subroutine
1.
We recommend that you initialize a H register to either "0" or "4"
2.
Do not write the instructions CALLL (PAGE + CALL) or JPL (PAGE + JP) to the reset address 0F00H. In
other words, do not use a PAGE instruction at 0F00H.
3.
Turn off the LED output pin.
4.
To reduce current consumption, do not set the option output pin to active state.
5.
Pre-set the remocon carrier frequency (to fxx/12, fxx/8, and so on) before remocon signal transmission.
6.
Because the program is initialized by an auto-reset or Halt mode release, even in normal operating state, do
not pre-set all RAM data. If necessary, pre-set only the RAM area you need.
7.
Be careful to control output pin status because some pins are automatically changed to active state.
8.
To enter Halt mode, the internal port, IP2.12, should be set to high level and all of the input pins should be
set to normal state.
9.
To release Halt mode, an active level signal is supplied to input pins. If pulse width is less than 9 ms at
fxx = 455 kHz, nothing happens and program re-enters Halt mode. That is, the external circuit should
maintain the input pulse over a 9-ms interval in order to release Halt mode. After Halt mode is released, the
hardware is reset. The hardware reset sends all internal and external output pins low (except P2.0 in
S3C1850/C1860) and clears the stack to zero. However, H,L and A registers retain their previous status.
10. If a rising edge is not generated at IP2.0, reset signal occurs every 288 ms at fxx = 455 kHz. To prevent an
auto-reset, IP2.0 should be forced low and then high at regular intervals (within 288 ms at fxx = 455 kHz).
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