
I-88
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
Selects the timing for reading in the serial data input.
When "1" is written:
Rising edge of SCLK
When "0" is written:
Falling edge of SCLK
Read-out:
Valid
Selects whether the fetching for the serial input data to
registers (SD0–SD7) at the rising edge (at "1" writing) or
falling edge (at "0" writing) of the SCLK signal.
Pay attention if the synchtonous clock goes into reverse
phase (SCLK
→ SCLK) through the mask option.
SCLK rising = SCLK falling, SCLK falling = SCLK rising
When the internal clock is selected as the synchronous
clock (SCLK), a hazard occurs in the synchronous clock
(SCLK) when data is written to register SE2.
The input data fetching timing may be selected but output
timing for output data is fixed at SCLK rising edge.
At initial reset, falling edge of SCLK (SE2 = "0") is selected.
This is the interrupt mask register of the serial interface.
When "1" is written:
Enabled
When "0" is written:
Masked
Read-out:
Valid
At initial reset, this register is set to "0" (mask).
This is the interrupt factor flag of the serial interface.
When "1" is read out:
Interrupt has occurred
When "0" is read out:
Interrupt has not occurred
Writing:
Invalid
From the status of this flag, the software can decide whether
the serial interface interrupt.
The interrupt factor flag is reset when it has been read out.
Note, however, that even if the interrupt is masked, this flag
will be set to "1" after the 8 bits data input/output.
Be sure that the interrupt factor flag reading is done with
the interrupt in the DI status (interrupt flag = "0").
At initial reset, this flag is set to "0".
SE2:
Clock edge selection
register
(F2HD1)
EISIO:
Interrupt mask register
(F2HD0)
ISIO:
Interrupt factor flag
(F3HD0)