
II-114
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 7: SUMMARY OF NOTES
(1) Write to the interrupt mask registers only in the DI status
(interrupt flag = "0"). Writing in the EI status can cause
an error.
(2) Even when the interrupt mask registers (ETI, EISWIT) are
set to "0", the interrupt factor flags (TI, SWIT) of the clock
timer and stopwatch counter can be set when the timing
conditions are established.
(3) When an interrupt is generated, three words of RAM are
used; also, it takes 12 cycles of the CPU system clock
until the value of the interrupt vector is set in the pro-
gram counter.
(4) When an interrupt occurs, the DI status (interrupt flag =
"0") comes into effect automatically.
(5) Read the interrupt factor flags only in the DI status
(interrupt flag = "0"). Reading out in the EI status can
cause an error.
When the watchdog timer is used for the reset function, the
software must reset the watch dog timer within 3 seconds.
In this case, timer data (WD0–WD2) cannot be used for
timer applications.
(1) It takes at least 5 ms from the time the OSC3 oscillation
circuit goes ON until the oscillation stabilizes. Conse-
quently, when switching the CPU operation clock from
OSC1 to OSC3, do this after a minimum of 5 ms have
elapsed since the OSC3 oscillation went ON.
Further, the oscillation stabilization time varies depend-
ing on the external oscillator characteristics and condi-
tions of use, so allow ample margin when setting the wait
time.
(2) When switching the clock from OSC3 to OSC1, use a
separate instruction for switching the OSC3 oscillation
OFF.
(3) To lessen current consumption, keep OSC3 oscillation
OFF except when the CPU must be run at high speed.
Also, with S1C62N33/62L33, keep OSCC fixed to "0".
– Interrupt and HALT
– OSC3
– Watchdog Timer