
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-109
CHAPTER 5: PERIPHERAL CIRCUITS (Serial Interface)
Programming notes
(1) When using the serial interface in the master mode, the
synchronous clock uses the CPU system clock. Accord-
ingly, do not change the system clock (fosc1
fosc3)
while the serial interface is operating.
(2) Perform data writing/reading to data registers SD0–SD7
only while the serial interface is halted (i.e., the synchro-
nous clock is neither being input or output).
(3) As a trigger condition, it is required that data writing or
reading on data registers SD0–SD7 be performed prior to
writing "1" to SCTRG. (The internal circuit of the serial
interface is initiated through data writing/reading on
data registers SD0–SD7.) Supply trigger only once every
time the serial interface is placed in the RUN state. More-
over, when the synchronous clock SCLK is external clock,
start to input the external clock after the trigger.
(4) If the bit data of SE2 changes while SCLK is in the master
mode, a hazard will be output to the SCLK pin. If this
poses a problem for the system, be sure to set the SCLK
to the external clock mode if the bit data of SE2 is to be
changed.
(5) Reading the interrupt factor flag (ISIO) can be done only
in the DI status (interrupt flag = "0"). Reading during EI
status (interrupt flag = "1") will cause malfunction.
(6) Writing the interrupt mask register (EISIO) can be done
only in the DI status (interrupt flag = "0"). Writing during
EI status (interrupt flag = "1") will cause malfunction.
(7) SCTRG resides in the same bit at the same address as
SIOF, and one or the other is selected by write or read
operation. When writing a "1" to SCTRG use the OR
command, and when writing a "0" use the AND com-
mand. No other commands should be used for this
purpose.