
S1C62N33 TECHNICAL HARDWARE
EPSON
I-77
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)
(1) It takes 100 s from the time the SVD circuit goes ON
until a stable result is obtained. For this reason, keep the
following software notes in mind:
When the CPU system clock is fosc1
1. When detection is done at HVLD
After writing "1" on HVLD, read the SVDDT after 1
instruction has passed.
2. When detection is done at SVDON
After writing "1" on SVDON, write "0" after at least
100 s has lapsed (possible with the next instruc-
tion) and then read the SVDDT.
When the CPU system clock is fosc3 (in case of
S1C62A33 only)
1. When detection is done at HVLD
After writing "1" on HVLD, read the SVDDT after 0.6
sec has passed. (HVLD holds "1" for at least 0.6 sec)
2. When detection is done at SVDON
Before writing "1" on SVDON, write "1" on HVLD
first; after at least 100 s has lapsed after writing
"1" on SVDON, write "0" on SVDON and then read
the SVDDT.
(2) SVDON resides in the same bit at the same address as
SVDDT, and one or the other is selected by write or read
operation. When writing a "1" to SVDON use the OR
command, and when writing a "0" use the AND command.
No other commands should be used for this purpose.
(3) Select one of the following software processing to return
to the normal mode after a heavy load has been driven in
the heavy load protection mode (S1C62L33).
After heavy load drive is completed, return to the
normal mode after at least one second has elapsed.
After heavy load drive is completed, switch SVD ON
and OFF (at least 100 s is necessary for the ON
status) and then return to the normal mode.
The S1C62N33/62A33 returns to the normal mode after
driving a heavy load without special software processing.
(4) When the SVD is to be turned on during operation in the
heavy load protection mode, limit the ON time to 10 ms
per second of operation time.
Programming notes