
S1C62N33 TECHNICAL HARDWARE
EPSON
I-63
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter)
SWL0–SWL3:
Stopwatch counter
1/100 sec (71H)
Data (BCD) of the 1/100 sec column of the stopwatch coun-
ter can be read out. These four bits are read-only, and
cannot be used for writing operations.
At initial reset, the counter data is set to "0H".
Data (BCD) of the 1/10 sec column of the stopwatch counter
can be read out. These four bits are read-only, and cannot
be used for writing operations.
At initial reset, the counter data is set to "0H".
These registers are used to select whether to mask the
stopwatch counter interrupt.
When "1" is written:
Enabled
When "0" is written:
Masked
Read-out:
Valid
The interrupt mask registers (EISWIT0, EISWIT1) are used
to separately select whether to mask the 10 Hz and 1 Hz
interrupts.
Writing to the interrupt mask registers can be done only in
the DI status (interrupt flag = "0").
At initial reset, these registers are both set to "0".
These flags indicate the status of the stopwatch counter
interrupt.
When "1" is read out:
Interrupt has occurred
When "0" is read out:
Interrupt has not occurred
Writing:
Invalid
The interrupt factor flags (SWIT0, SWIT1) correspond to the
10 Hz and 1 Hz interrupts respectively. With these flags, the
software can judge whether a stopwatch counter interrupt
has occurred. However, regardless of the interrupt mask
register setting, these flags are set to "1" by the counter
overflow.
These flags are reset when read out by the software. Also,
read-out is only possible in the DI status (interrupt flag =
"0").
At initial reset, these flags are set to "0".
SWIT0, SWIT1:
Interrupt factor flag
(7AHD0 and D1)
EISWIT0, EISWIT1:
Interrupt mask register
(76HD0 and D1)
SWH0–SWH3:
Stopwatch counter
1/10 sec (72H)