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參數(shù)資料
| 型號(hào)： | S1C62A33D |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 0.6 MHz, MICROCONTROLLER, UUC86 |
| 封裝： | DIE-86 |
| 文件頁(yè)數(shù)： | 271/280頁(yè) |
| 文件大?。?/td> | 1603K |
| 代理商： | S1C62A33D |
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I-76
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)
When SVD sampling is done with HVLD set to "1", the
results are written to the SVDDT latch in the timing as
follows:
(1) As soon as the time has elapsed for one instruction cycle
immediately following HVLD = "1"
(2) Immediately on completion of sampling at cycles of 2 Hz
output by the clock timer while HVLD = "1"
Consequently, the SVDDT latch data is written immediately
after HVLD is set to "1", and at the same time the new
detection result is written in 2 Hz cycles.
When "0" is written:
SVD detection OFF
When "1" is written:
SVD detection ON
When "0" is read out:
Source voltage (VDD–VSS)
is higher than SVD set value
When "1" is read out:
Source voltage (VDD–VSS)
is lower than SVD set value
Note that the function of this bit when written is different to
when read out.
When this bit is written to, ON/OFF of the SVD detection
operation is controlled; when this bit is read out, the result of
the SVD detection (contents of SVDDT latch) is obtained.
Appreciable current is consumed during operation of SVD
detection, so keep SVD detection OFF except when necessary.
When SVDON is set to "1", SVD detection is executed. As
soon as SVDON is reset to "0" the detection result is loaded
to the SVDDT latch. To obtain a stable SVD detection result,
the SVD circuit must be set to ON with at least 100 s.
Hence, to obtain the SVD detection result, follow the pro-
gramming sequence below.
0. Set HVLD to "1" (only when the CPU system clock is
fosc3 in S1C62A33)
1. Set SVDON to "1"
2. Maintain at 100 s minimum
3. Set SVDON to "0"
4. Read out SVDDT
5. Set HVLD to "0" (only when the CPU system clock is
fosc3 in S1C62A33)
However, when a crystal oscillation clock (fosc1) is selected
for the CPU system clock in S1C62N33, S1C62L33, and
S1C62A33, the instruction cycles are long enough, so that
there is no need for concern about maintaining 100 s for
the SVDON = "1" with the software.
SVDON/SVDDT:
SVD detection/SVD data
(76HD2)
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