S1C62N33 TECHNICAL HARDWARE
EPSON
I-81
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
Data input/output
and interrupt func-
tion
The serial interface of S1C62N33 can input/output data via
the internal 8 bits shift register. The shift register operates
by synchronizing with either the synchronous clock output
from SCLK terminal (master mode), or the synchronous
clock input to SCLK (slave mode).
The serial interface generates interrupt on completion of the
8 bits serial data input/output. Detection of serial data
input/output is done by the counting of the synchronous
clock (SCLK); the clock completes input/output operation
when 8 counts (equivalent to 8 cycles) have been made and
then generates interrupt.
The serial data input/output procedure data is explained
below:
(1) Serial data output procedure and interrupt
The S1C62N33 serial interface is capable of outputting
parallel data as serial data, in units of 8 bits.
By setting the parallel data to 4 bits registers SD0–SD3
(address F0H) and SD4–SD7 (address F1H) individually
and writing "1" to SCTRG bit (address 77HD3), it syn-
chronizes with the synchronous clock and serial data is
output at the SOUT terminal. The synchronous clock
used here is as follows: in the master mode, internal
clock which is output to the SCLK terminal while in the
slave mode, external clock which is input from the SCLK
terminal. The serial output of the SOUT termina changes
with the rising edge of the clock that is input or output
from the SCLK terminal.
The serial data to the built-in shift register is shifted with
the rising edge of the SCLK signal when SE2 bit (address
F2HD1) is "1" and is shifted with the falling edge of the
SCLK signal when SE2 bit (address F2HD1) is "0".
When the output of the 8 bits data from SD0 to SD7 is
completed, the interrupt factor flag ISIO (address
F3HD0) is set to "1" and interrupt is generated. Moreo-
ver, the interrupt can be masked by the interrupt mask
register EISIO (address F2HD0).