I-82
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
(2) Serial data input procedure and interrupt
The S1C62N33 serial interface is capable of inputting
serial data as parallel data, in units of 8 bits.
The serial data is input from the SIN terminal, synchro-
nizes with the synchronous clock, and is sequentially
read in the 8 bits shift register. As in the above item (1),
the synchronous clock used here is as follows: in the
master mode, internal clock which is output to the SCLK
terminal while in the slave mode, external clock which is
input from the SCLK terminal.
The serial data to the built-in shift register is read with
the rising edge of the SCLK signal when SE2 bit is "1"
and is read with the falling edge of the SCLK signal when
SE2 bit is "0". Moreover, the shift register is sequentially
shifted as the data is fetched.
When the input of the 8 bits data from SD0 to SD7 is
completed, the interrupt factor flag ISIO is set to "1" and
interrupt is generated. Moreover, the interrupt can be
masked by the interrupt mask register EISIO. Note,
however, that regardless of the setting of the interrupt
mask register, the interrupt factor flag is set to "1" after
input of the 8 bits data.
The data input in the shift register can be read from data
registers SD0–SD7 by software.