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| 型號： | QUADS68040UM_D |
| 英文描述： | M68360QUADS-040 User＇s Manual |
| 中文描述： | M68360QUADS - 040使用手冊 |
| 文件頁數(shù)： | 57/86頁 |
| 文件大?。?/td> | 1351K |
| 代理商： | QUADS68040UM_D |
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Freescale Semiconductor, Inc.
SUPPORT INFORMATION
57
6.
The Host detects the ADS_ACK signal and negates the HOST_REQ signal (data buffer is
disabled).
The M68360QUADS-040 detects the negation of HOST_REQ signal and negates
ADS_ACK to end the cycle.
7.
FIGURE B-2 Host Write to M68360QUADS-040
1
B.3.2
Write Cycle from M68360QUADS-040 to Host
The signal handshake during an M68360QUADS-040 to Host write cycle is shown in FIGURE B-3. The
sequence of events is as follows:
1.
The M68360QUADS-040 places a data byte on the parallel port data bus (buffer disabled)
and asserts the ADS_REQ signal (the ADS_REQ signal will not appear on the port until
the board is selected by the Host).
2.
The Host polls each M68360QUADS-040 address and detects the ADS_REQ signal from
the requesting board. The Host asserts the HST_ACK signal in response, which enables
the data buffer in the M68360QUADS-040.
3.
The M68360QUADS-040 negates the ADS_REQ signal. The data appears on the bus as
long as the HST_ACK signal is asserted.
4.
The Host reads the data.
5.
The Host negates the HST_ACK signal to end the cycle. The M68360QUADS-040 ends
the cycle.
ADS_SEL(0:2)
HOST_REQ
ADS_ACK
PD(0:7)
ADDRESS VALID
2
3
4
5
6
7
DATA VALID
F
For More Information On This Product,
Go to: www.freescale.com
n
.
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