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| 型號： | QUADS68040UM_D |
| 英文描述： | M68360QUADS-040 User＇s Manual |
| 中文描述： | M68360QUADS - 040使用手冊 |
| 文件頁數(shù)： | 22/86頁 |
| 文件大?。?/td> | 1351K |
| 代理商： | QUADS68040UM_D |
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Freescale Semiconductor, Inc.
OPERATING INSTRUCTIONS
22
bus fault monitor and to enable the bus monitor function to respond after 1 K clock cycles in the slave
QUICC.
3.4.7
Global Memory Register
The global memory register (GMR) contains selections for the memory controller of the slave QUICC. The
GMR must be initialized according to the size and the access time of the DRAM SIMM installed on the
M68360QUADS as follows:
For 60, 70, 80 & 100 nsec DRAM type MCM36256 or MCM36100, the GMR must be initialized to
’18A40000’.
For 60, 70, 80 & 100 nsec DRAM type MCM36512 or MCM36200, the GMR must be initialized to
’0CA40000’.
The GMR defines the following parameters:
The DRAM refresh period is 15.36
μ
sec.
The DRAM refresh cycle length 4 clocks long.
The DRAM module port size is 32 bits.
No extra wait between 040 dram accesses (4 phase precharge time)
No extra wait between QUICC dram accesses (4 phase precharge time)
Same length QUICC DRAM reads / writes
Same length 040 SRAM reads / writes
Parity is disabled.
The CS~/RAS~ lines of the slave QUICC will not assert when accessing the CPU space.
Internal address multiplexing for the DRAM is disabled.
3.4.8
Base Register 0 and Option Register 0
Base register 0 (BR0) and Option register 0 (OR0) control the operation of CS0~ pin of the slave QUICC,
which serves as the Flash Prom chip-select.
BR0 is initialized to 00000001 to determine the following:
Base address - 0.
No burst support for EC040 access
Parity disabled
3.4.9
Base Register 1 and Option Register 1
Base register 1 (BR1) and Option register 1 (OR1) control the operation of RAS1~ pin of the slave QUICC.
This pin is connected to the RAS signal of the first bank in the DRAM module.
BR1 must be initialized to ’00400021’, regardless of the type and the access time of the DRAM to establish
the following:
Base address 400000.
Burst support for EC040 access
Parity disabled
OR1 must be initialized according to the type of the DRAM SIMM installed on the M68360QUADS-040 as
follows:
F
For More Information On This Product,
Go to: www.freescale.com
n
.
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