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| 型號： | QUADS68040UM_D |
| 英文描述： | M68360QUADS-040 User＇s Manual |
| 中文描述： | M68360QUADS - 040使用手冊 |
| 文件頁數(shù)： | 38/86頁 |
| 文件大?。?/td> | 1351K |
| 代理商： | QUADS68040UM_D |
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Freescale Semiconductor, Inc.
FUNCTIONAL DESCRIPTION
38
Port A is 16 pins port. TABLE 4-2 describes the configuration of port A.
4.11.8.2
Slave QUICC Port B
TABLE 4-2 Port A Pins Description
Pin
Pin Name
Description
0
EEST RX
This pin is connected to the receive data output of the EEST. It is configured as the
receive data of SCC1 in the slave QUICC.
1
EEST TX
This pin is connected to the transmit data input of the EEST. It is configured as the
transmit data of SCC1 in the slave QUICC.
2
SIA RX
This pin is connected to the receive data output of the SIA. It is configured as the
receive data of SCC2 in the slave QUICC.
3
SIA TX
This pin is connected to the transmit data input of the SIA. It is configured as the
transmit data of SCC2 in the slave QUICC.
4
RS-232 RX
This pin is connected to the receive data output of the RS-232 transceiver U23. It is
configured as the receive data of SCC3 in the slave QUICC.
5
RS-232 TX
This pin is connected to the transmit data input of the RS-232 transceiver U23. It is
configured as the transmit data of SCC3 in the slave QUICC.
6
PA6
This pin is connected to The expansion connector (P11) and may be utilized for
user’s applications.
7
PA7
This pin is connected to The expansion connector (P11) and may be utilized for
user’s applications.
8
EEST TCLK
This pin is connected to the transmit clock output of the EEST. It is configured as the
transmit clock of SCC1 in the slave QUICC.
9
EEST RCLK
This pin is connected to the receive clock output of the EEST. It is configured as the
receive clock of SCC1 in the slave QUICC.
10
SIA TCLK
This pin is connected to the transmit clock output of the SIA. It is configured as the
transmit clock of SCC2 in the slave QUICC.
11
SIA RCLK
This pin is connected to the receive clock output of the SIA. It is configured as the
receive clock of SCC2 in the slave QUICC.
12
ADS ACK~
This pin is connected to the ADI port signal ADS_ACK through the buffer U1. It is
configured as output pin in the slave QUICC.
13
ADS REQ~
This pin is connected to the ADI port signal ADS_REQ through the buffer U1. It is
configured as output pin in the slave QUICC.
14
ADS G~
This pin is connected to the ADI port logic. It is configured as output pin in the slave
QUICC, and it is used by the ADI logic to control the ADI data transceiver.
15
ADS INT~
This pin is connected to the ADI port signal ADS_INT through the buffer U1. It is
configured as output pin in the slave QUICC, and it is also used by the ADI logic to
interrupt the host computer.
F
For More Information On This Product,
Go to: www.freescale.com
n
.
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