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參數(shù)資料
| 型號： | QUADS68040UM_D |
| 英文描述： | M68360QUADS-040 User＇s Manual |
| 中文描述： | M68360QUADS - 040使用手冊 |
| 文件頁數(shù)： | 23/86頁 |
| 文件大?。?/td> | 1351K |
| 代理商： | QUADS68040UM_D |
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Freescale Semiconductor, Inc.
OPERATING INSTRUCTIONS
23
For MCM36256 or MCM36512 types:
For 100 nsec access time - 3FF00001
For 80 nsec or 70 nsec access time - 2FF00001
For 60 nsec access time 1FF00001
For MCM36100 or MCM36200 types:
For 100 nsec access time - 3FC00001
For 80 nsec or 70 nsec access time - 2FC00001
For 60 nsec access time 1FC00001
NOTE
To ensure proper operation of the DRAM, its RAS signal
should be asserted and negated 8 times after power-up.
Therefore after power-up, each dram bank should be read 8
times to comply with the requirement above.
Base Register 2 and Option Register 2
3.4.10
Base register 2 (BR2) and Option register 2 (OR2) control the operation of RAS2~ pin of the slave QUICC.
This pin is connected to the second
1
bank of the DRAM module.
BR2 must be initialized according to the type of DRAM SIMM installed on the M68360QUADS-040 as
follows:
For MCM36256 or MCM36100 types, BR2 is not initialized leaving RAS2 inactive.
For MCM36512 type, BR2 must be initialized to 500021
For MCM36200 type, BR2 must be initialized to 800021
OR2 initialization depends also of the DRAM SIMM type installed on the M68360QUADS-040 as to the
following:
For MCM36256 or MCM36512 types:
For 100 nsec access time - 3FF00001
For 80 nsec or 70 nsec access time - 2FF00001
For 60 nsec access time 1FF00001
For MCM36100 or MCM36200 types:
For 100 nsec access time - 3FC00021
For 80 nsec or 70 nsec access time - 2FC00001
For 60 nsec access time 1FC00001
3.4.11
Base Register 3 and Option Register 3
Base register 3 (BR3) and Option register 3 (OR3) control the operation of CS3~ pin of the slave QUICC,
which controls the first bank of the Bursting SRAM. BR3 must be initialized to ’003C0021’, and OR3 must
be initialized to ’1FFE0000’ to obtain the memory map as described in TABLE 3-2.
3.4.12
Base Register 4 and Option Register 4
Base register 4 (BR4) and Option register 4 (OR4) control the operation of CS4~ pin of the slave QUICC,
which controls the second bank of the Bursting SRAM. BR4 must be initialized to ’003E0021’, and OR4
must be initialized to ’1FFE0000’ to obtain the memory map as described in TABLE 3-2.
1. If available
F
For More Information On This Product,
Go to: www.freescale.com
n
.
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