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| 型號： | QUADS68040UM_D |
| 英文描述： | M68360QUADS-040 User＇s Manual |
| 中文描述： | M68360QUADS - 040使用手冊 |
| 文件頁數(shù)： | 45/86頁 |
| 文件大?。?/td> | 1351K |
| 代理商： | QUADS68040UM_D |
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Freescale Semiconductor, Inc.
SUPPORT INFORMATION
45
5.2.9
Connector P9 Interconnect Signals
Connector P9 is a triple-row, 96 pin, male DIN connector. P8 and P9 Logic-Analyzer connectors provide
most of the signals of the slave QUICC and the MC68EC040’s. TABLE 5-1 describes the P9 connector
signals.
a. Quicc’s A28 - A31 are used as Write Enables, therefore not connected to EC040’s corresponding signals
C4
C5
C6 - C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
TT0
GND
SIZ0 - SIZ1
BRQ~
BGQ~
BB~
AS~
GND
TT1
R/W~
GND
LOCK~
DD2~
TBI~
TA~
TEA~
VCC
RSTH~
RSTS~
PERR~
VCC
TS~
WE0~
WE1~
GND
WE2~
GND
WE3~
Transfer Type signal 0 pin of the EC040
M68360QUADS-040 board Ground.
EC040’s Access Size indicators 0 to 1
Quicc’s Bus Request
Quicc’s Bus Grant
Bus Busy
Quicc’s Address Strobe
Board Ground
EC040’s Transfer Type 1
Read / Write
Board Ground
EC040 Locked (RMW) Cycle indicator
Quicc’s RAS Double Drive 2
EC040’s Transfer Burst Inhibit
EC040’s Transfer Acknowledge
EC040’s Transfer Error Acknowledge
Board’s VCC plane
Hard reset pin of the QUICC
Soft reset pin of the QUICC
Parity error pin of the QUICC
Board’s VCC plane
EC040‘s Transfer Start
Quicc’s Write Enable 0
Quicc’s Write Enable 1
Board’s Ground
Quicc’s Write Enable 2
Board’s Ground
Quicc’s Write Enable 3
TABLE 5-9 Connector P9 Interconnect Signals
Pin No.
Signal Name
Description
A1
A2
A3
CLK4
GND
SIA_RX
Buffered System clock
Board’s Ground
SIA Receive Data. Also SCC2’s Receive Data
TABLE 5-8 Connector P8 Interconnect Signals
Pin No.
Signal Name
Description
F
For More Information On This Product,
Go to: www.freescale.com
n
.
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