- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361330 > QUADS68040UM_D M68360QUADS-040 User＇s Manual PDF資料下載
參數(shù)資料
| 型號(hào)： | QUADS68040UM_D |
| 英文描述： | M68360QUADS-040 User＇s Manual |
| 中文描述： | M68360QUADS - 040使用手冊(cè) |
| 文件頁數(shù)： | 29/86頁 |
| 文件大?。?/td> | 1351K |
| 代理商： | QUADS68040UM_D |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁當(dāng)前第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁
Freescale Semiconductor, Inc.
FUNCTIONAL DESCRIPTION
29
FIGURE 4-1 Arbitration Scheme:
Since the level of priority associated with the BR~ input is lower (8) than the SDMA’s, no use is done with
the BCLRO~ signal of the QUICC is not used. In sake of simplicity, no use is done with the IPEND~ is not
used as a BCLI~ for the QUICC.
4.5
System Utilities
The slave QUICC provides the M68360QUADS-040 with the following system utilities, usually provided by
external logic:
1.
Breakpoint generation
2.
Bus Monitor (also known as hardware watch-dog)
3.
Spurious Interrupt Monitor
4.
Software watch-dog
5.
Periodic Interval Timer (also known as real-time-clock or tic-timer)
4.5.1
Breakpoints Generator
The QUICC may be used as a hardware breakpoint generator for the 68EC040. When the 68EC040
initiates a bus cycle by asserting TS~, the breakpoint logic compares the cycle’s address to the address in
the BKAR and to the access attributes in the BKCR. If there is a match, the BKPTO* signal is asserted by
the QUICC. Since TS~ is asserted only at the beginning of the cycle, no address comparison is done for
the rest of the access (burst access). The BKPTO* of the slave QUICC is wired via a jumper to generate
a non-maskable interrupt on level 7.
If the EC040 performs a breakpoint instruction, the QUICC will not respond, letting the bus monitor
terminate the cycle with TEA~.
4.5.2
Bus Monitor
The QUICC monitors for unterminated bus cycles, performed either by the 68EC040 or by the QUICC’s
internal masters. If a bus cycle fails to terminate with TA~ or TEA~ (DSACK~ or BERR) during a
programmable period of time, the bus monitor terminates the cycle, by asserting TEA~ for the EC040 (or
BERR~ for an internal master). Upon reset, the bus monitor is initialized to expire after 1K system clocks
(CLKO1 clocks).
QUICC
EC040
BR
BG
BR
BG
E
J10
J9
F
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| QUICK_REF_FAQ | FAQs and Recommendations for an AMD Athlon? Processor-Based Computer |
| QUICK-CHIP2 | ASIC |
| QUICK-CHIP2K | ASIC |
| QUICK-CHIP6 | ASIC |
| QUICK-CHIP7 | ASIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QUAL-MANU-01 | 制造商:BEL 制造商全稱:Bel Fuse Inc. 功能描述:QUALITY MANUAL |
| QUARTER-BRICKSERIES | 制造商:EMERSON-NETWORKPOWER 制造商全稱:Emerson Network Power 功能描述:High Current, High Efficiency, Low Profile |
| QUATRO4050 | 制造商:ZORAN 制造商全稱:ZORAN 功能描述:Programmable SOC Solution for Printers and All-in-Ones |
| QUATRO4100 | 制造商:ZORAN 制造商全稱:ZORAN 功能描述:Programmable SOC Solution for Printing Appliances |
| QUATRO4110 | 制造商:ZORAN 制造商全稱:ZORAN 功能描述:Programmable SOC Solution for Printing Appliances |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。