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參數(shù)資料
| 型號： | QL8325 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| 中文描述： | 低功耗FPGA配合力性能密度和嵌入式內(nèi)存 |
| 文件頁數(shù)： | 9/49頁 |
| 文件大?。?/td> | 739K |
| 代理商： | QL8325 |
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Preliminary
8
NOTE:
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The input frequency can range from 16 MHz to 300 MHz, while output frequency ranges from
25 MHz to 250 MHz. When you add PLLs to your top-level design, be sure that the PLL mode
matches your desired input and output frequencies.
"
< =
summarizes the key signals in QuickLogic's PLLs.
NOTE:
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PLL_HF
Same as input
66 MHz–150 MHz
66 MHz–150 MHz
PLL_LF
Same as input
25 MHz–133 MHz
25 MHz–133 MHz
PLL_MULT2HF
2x
50 MHz–125 MHz
100 MHz–250 MHz
PLL_MULT2LF
2x
16 MHz–50 MHz
32 MHz–100 MHz
PLL_DIV2HF
1/2x
100 MHz–250 MHz
50 MHz–125 MHz
PLL_DIV2LF
1/2x
50 MHz–100 MHz
25 MHz–50 MHz
PLL_MULT4
4x
16 MHz–40 MHz
64 MHz–160 MHz
PLL_DIV4
1/4x
100 MHz–300 MHz
25 MHz–75 MHz
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PLLCLK_IN
Input clock signal
PLL_RESET
Active High Reset
If PLL_RESET is asserted, then CLKNET_OUT and
PLLPAD_OUT are reset to 0. This signal must be asserted and then released
in order for the LOCK_DETECT to work.
ONn_OFFCHIP
PLL output
This signal selects whether the PLL will drive the internal clock
network or be used off-chip. This is a static signal, not a dynamic signal.
Tied to GND = outgoing signal drives internal gates.
Tied to VCC = outgoing signal used off-chip.
CLKNET_OUT
Out to internal gates
This signal bypasses the PLL logic before driving the
internal gates. Note that this signal cannot be used in the same quadrant where
the PLL signal is used (PLLCLK_OUT).
PLLCLK_OUT
Out from PLL to internal gates
This signal can drive the internal gates after
going through the PLL. For this to work, ONn_OFFCHIP must be tied to GND.
PLLPAD_OUT
Out to off-chip
This outgoing signal is used off-chip. For this to work,
ONn_OFFCHIP signal must be tied to VCC.
LOCK_DETECT
Active High Lock detection signal
NOTE: For simulation purposes, this
signal gets asserted after 10 clock cycles. However, it can take a maximum of
200 clock cycles to sync with the input clock upon release of the RESET signal.
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