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參數(shù)資料
| 型號(hào)： | QL8325 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| 中文描述： | 低功耗FPGA配合力性能密度和嵌入式內(nèi)存 |
| 文件頁數(shù)： | 16/49頁 |
| 文件大?。?/td> | 739K |
| 代理商： | QL8325 |
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Preliminary
9
Express lines run the length of the programmable logic uninterrupted. Each of these lines has a
higher capacitance than a quad, dual, or short wire, but less capacitance than shorter wires
connected to run the length of the device. The resistance will also be lower because the express
wires don't require the use of "pass" links. Express wires provide higher performance for long
routes or high fan-out nets.
Distributed networks are described in the clock/control section. These wires span the
programmable logic and are driven by "column clock" buffers. All clock network pin buffers (both
Dedicated and Global) are hard wired to individual sets of column clock buffers.
,&/!")!*
The Eclipse-II
family of devices features a global power-on reset. This reset is hardwired to all
registers and resets them to Logic ‘0’ upon power-up of the device. In QuickLogic devices, the
aynchronous Reset input to flip-flops has priority over the Set input; therefore, the Global POR
will reset all flip-flops during power-up. If you want to set the flip-flops to Logic ‘1’, you must assert
the “Set” signal after the Global POR signal has been deasserted.
'/*,
&&
Power consumption of the two smaller Eclipse-II devices can be reduced significantly by de-
activating the charge pumps inside the architecture. By applying 3.3 V to the Vpump pin, the
internal charge pump is de-activated—this effectively reduces the dynamic power consumption of
the device. Users who have a 3.3 V supply available in their system should take advantage of this
low power feature by tying the Vpump pin to 3.3 V. Otherwise, if a 3.3 V supply is not available,
this pin should be tied to ground.
VCC
Power-on
Reset
Q
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0
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