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參數(shù)資料
| 型號(hào)： | QL80FC-APQ208I |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁(yè)數(shù)： | 1/21頁(yè) |
| 文件大?。?/td> | 757K |
| 代理商： | QL80FC-APQ208I |
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QuickLogic QL80FC Programmable Fibre Channel ENDEC
QL80FC - QuickFC
TM
Rev A
QL80FC - QuickFC
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ANSI Fibre Channel (FC) compatibility
Data rates up to 2.5 Gb/s supported
2.5Gb/s Simplex (200 MByte/s) or Duplex
(400 MByte/s) Mode
Compatible with standard SERDES components
32 bit synchronous FIFO system interface
Tx and Rx internal FIFO for system applications
without external FIFOs
Selectable 20-bit/10-bit encoded transmission
character interface to SERDES
8b/10b Encoding/Decoding
CRC Calculation and checking per FC standard
Fibre Channel Loss of Synchronization (LOS) state
machine
Support for arbitrated loops
IntraFrame idles support for proprietary links
“Raw” data path for the injection of encoding and
CRC errors into the bitsteam for use in testing link
error handling functions
3.3V operating voltage
3.3V CMOS I/O, 5.0V CMOS tolerant inputs
208 PQFP and 456 PBGA packages available
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Extended Features
Extended features that can be designed into the user
customizable logic:
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Fibre Channel Link Control State Machine (LCSM)
RRDY credit management for link flow control
Microprocessor interface to configure various link
modes
BIST functions support link bit error rate
measurements
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F
EATURES
E
XTENDED
F
EATURES
Dual Port SRAM
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22 blocks (total of 25,344 bits) of dual-port RAM
Configurable as RAM, ROM or FIFO
Can be configured as two internal FIFOs of up to
352 x 36 in size
Configurable RAM array sizes (by 2, 4, 9, 18)
<5ns access times, 160+Mhz FIFOs
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High Speed Customizable Logic
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Up to 269 customizable I/O pins
751 Logic cells
300 MHz 16-bit counters, 400 MHz Data paths
Mux-Based architecture; non-volatile technology
Completely customizable for any digital application
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Fibre Channel Block Diagram
D
UAL
P
ORT
SRAM
H
IGH
S
PEED
C
USTOMIZABLE
L
OGIC
RAM Blocks
22 Blocks (25K bits)
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Fibre Channel ENDEC
Customizable
Logic Cells
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Transmit
Receive
10 bit/20 bit
10 bit/20 bit
IO Pins
相關(guān)PDF資料 |
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| QL80FC | Programmable Fibre Channel ENDEC(可編程光纖信道編解碼器) |
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| QL82SD-PB516 | 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
| QL82SD-PQ208 | 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
| QL82SD-PS484 | 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| QL8150 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| QL8250 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| QL8250-6PQN208C-5690 | 制造商:QuickLogic Corporation 功能描述: |
| QL8250-6PQN208C-5691 | 制造商:QuickLogic Corporation 功能描述: |
| QL82SD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
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