參數(shù)資料
型號(hào): QL8325
廠商: Electronic Theatre Controls, Inc.
英文描述: LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
中文描述: 低功耗FPGA配合力性能密度和嵌入式內(nèi)存
文件頁數(shù): 26/49頁
文件大?。?/td> 739K
代理商: QL8325
Preliminary
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t
SWA
WA setup time to WCLK: time the WRITE ADDRESS must be stable before the
active edge of the WRITE CLOCK
0.675 ns
-
t
HWA
WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active
edge of the WRITE CLOCK
0 ns
-
t
SWD
WD setup time to WCLK: time the WRITE DATA must be stable before the active
edge of the WRITE CLOCK
0.654 ns
-
t
HWD
WD hold time to WCLK: time the WRITE DATA must be stable after the active edge
of the WRITE CLOCK
0 ns
-
t
SWE
WE setup time to WCLK: time the WRITE ENABLE must be stable before the active
edge of the WRITE CLOCK
0.623 ns
-
t
HWE
WE hold time to WCLK: time the WRITE ENABLE must be stable after the active
edge of the WRITE CLOCK
0 ns
-
t
WCRD
WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the
time when the data is available at RD
-
4.38 ns
tSWA
tSWD
tSWE
tHWA
tHWD
tHWE
tWCRD
old data
new data
WCLK
WA
WD
WE
RD
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