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參數(shù)資料
| 型號(hào)： | QL8325 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| 中文描述： | 低功耗FPGA配合力性能密度和嵌入式內(nèi)存 |
| 文件頁數(shù)： | 18/49頁 |
| 文件大?。?/td> | 739K |
| 代理商： | QL8325 |
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Preliminary
3
Bypass Instruction.
The Bypass instruction allows data to skip a device's boundary scan
entirely, so the data passes through the bypass register. The Bypass instruction allows users
to test a device without passing through other devices. The bypass register is connected
between the TDI and TDO pins, allowing serial data to be transferred through a device
without affecting the operation of the device.
@<,:''
BSDL-Boundary Scan Description Language
Machine-readable data for test equipment to generate testing vectors and software
BSDL files available for all device/ package combinations from QuickLogic
Extensive industry support available and ATVG (Automatic Test Vector Generation)
+-
There are two security links: one to disable reading logic from the array, and the second to disable
J TAG access to the device. Programming these optional links completely disables access to the
device from the outside world and provides an extra level of design security not possible in SRAM-
based FPGAs. The option to program these fuses is selectable via QuickWorks in the
Tools/Options/Device Programming window in SpDE.
+-
The flexibility link enables Power-Up loading of the Embedded RAM blocks. If the link is
programmed, the Power Up Loading state machine is activated during power-up of the device.
The state machine communicates with an external EPROM via the J TAG pins to download
memory contents into the on-chip RAM. If the link is not programmed, Power-Up Loading is not
enabled and the J TAG pins function as they normally would. The option to program this bit is
selectable via QuickWorks in the Tools/Options/Device Programming window in SpDE. For
more information on Power-Up Loading refer to QuickLogic Application Note 55.
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