參數(shù)資料
型號(hào)： QL8325
廠商： Electronic Theatre Controls, Inc.
英文描述： LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
中文描述： 低功耗FPGA配合力性能密度和嵌入式內(nèi)存
文件頁(yè)數(shù)： 8/49頁(yè)
文件大?。?/td> 739K
代理商： QL8325
Preliminary
3
9
illustrates a QuickLogic PLL.
&'
F
in
represents a very stable high-frequency input clock and produces an accurate signal reference.
This signal can either bypass the PLL entirely, thus entering the clock tree directly, or it can pass
through the PLL itself.
Within the PLL, a voltage-controlled oscillator (VCO) is added to the circuit. The external F
in
signal
and the local VCO form a control loop. The VCO is multiplied or divided down to the reference
frequency, so that a phase detector (the crossed circle in
9
If the phases of the external and local signals are not within the tolerance required, the phase
detector sends a signal through the charge pump and loop filter (
9
generates an error voltage to bring the VCO back into alignment, and the loop filter removes any
high frequency noise before the error voltage enters the VCO. This new VCO signal enters the
clock tree to drive the chip's circuitry.
) can compare the two signals.
). The charge pump
F
out
represents the clock signal emerging from the output pad (the output signal PLLPAD_OUT
is explained in
< =
). This clock signal is meaningful only when the PLL is configured for
external use; otherwise, it remains in high Z state.
Most QuickLogic products contain four PLLs. The PLL presented in
9
tree in the fourth quadrant of its FPGA. QuickLogic PLLs compensate for the additional delay
created by the clock tree itself, as previously noted, by subtracting the clock tree delay through the
feedback path.
controls the clock
For more specific information on the Phase Locked Loops, please refer to QuickLogic
Application Note 58.
-!'"
QuickLogic PLLs have eight modes of operation, based on the input frequency and desired output
frequency—
< 9
indicates the features of each mode.
vco
Filter
FIN
FOUT
+
-
1st Quadrant
2nd Quadrant
3rd Quadrant
4th Quadrant
Clock
Frequency Divide
Frequency Multiply
1
2
._
4
._
4
._
2
._
1
PLL Bypass
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