參數(shù)資料
型號(hào)： QL8325
廠(chǎng)商： Electronic Theatre Controls, Inc.
英文描述： LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
中文描述： 低功耗FPGA配合力性能密度和嵌入式內(nèi)存
文件頁(yè)數(shù)： 17/49頁(yè)
文件大小： 739K
代理商： QL8325
Preliminary
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Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design
challenges, one problem being the accessibility of test points. J TAG formed in response to this
challenge, resulting in IEEE standard 1149.1, the Standard Test Access Port and Boundary Scan
Architecture.
The J TAG boundary scan test methodology allows complete observation and control of the
boundary pins of a J TAG-compatible device through J TAG software. A Test Access Port (TAP)
controller works in concert with the Instruction Register (IR), which allow users to run three
required tests along with several user-defined tests.
J TAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse
subsystem tests for fuller verification of higher level system elements.
The 1149.1 standard requires the following three tests:
Extest Instruction.
The Extest instruction performs a PCB interconnect test. This test
places a device into an external boundary test mode, selecting the boundary scan register to
be connected between the TAP's Test Data In (TDI) and Test Data Out (TDO) pins. Boundary
scan cells are preloaded with test patterns (via the Sample/Preload Instruction), and input
boundary cells capture the input data for analysis.
Sample/Preload Instruction.
This instruction allows a device to remain in its functional
mode, while selecting the boundary scan register to be connected between the TDI and TDO
pins. For this test, the boundary scan register can be accessed via a data scan operation,
allowing users to sample the functional data entering and leaving the device.
TCK
TMS
TRSTB
RDI
TDO
Instruction Decode
&
Control Logic
Tap Controller
State Machine
(16 States)
Instruction Register
Boundary-Scan Register
(Data Register)
Mux
Bypass
Register
Mux
Internal
Register
I/O Registers
User Defined Data Register
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