參數(shù)資料
型號(hào)： QL8325
廠商： Electronic Theatre Controls, Inc.
英文描述： LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
中文描述： 低功耗FPGA配合力性能密度和嵌入式內(nèi)存
文件頁(yè)數(shù)： 35/49頁(yè)
文件大?。?/td> 739K
代理商： QL8325
Preliminary
65
&!'">"+
The basic power equation which best models power consumption is given below:
P
TOTAL
= 0.350 +
f
[0.0031
η
LC
+ 0.0948
η
CKBF
+ 0.01
η
CLBF
+ 0.0263
η
CKLD
+
0.543
η
RAM
+ 0.20
η
PLL
+ 0.0035
η
INP
+ 0.0257
η
OUTP
] (mW)
Where
η
LC
is the total number of logic cells in the design
η
CKBF
= # of clock buffers
η
CLBF
= # of column clock buffers
η
CKLD
= # of loads connected to the column clock buffers
η
RAM
= # of RAM blocks
η
PLL
= # of PLLs
η
INP
is the number of input pins
η
OUTP
is the number of output pins
NOTE:
&&&=1/&*L>B
&/'>""
'/2;,,
The following requirements must be met when powering up a device (refer to
64
):
When ramping up the power supplies keep (V
CCIO
-V
CC
)
MAX
≤
500 mV. Deviation from this
recommendation can cause permanent damage to the device.
V
CCIO
must lead V
CC
when ramping the device.
The power supply must be greater than or equal to 400 μs to reach V
CC
. Ramping to
V
CC
/V
CCIO
before reaching 400 μs can cause the device to behave improperly.
V
V
CCIO
V
CC
(V
CCIO
-V
CC
)
MAX
400 us
V
CC
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