參數(shù)資料
型號(hào)： QL8325
廠商： Electronic Theatre Controls, Inc.
英文描述： LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
中文描述： 低功耗FPGA配合力性能密度和嵌入式內(nèi)存
文件頁(yè)數(shù)： 39/49頁(yè)
文件大?。?/td> 739K
代理商： QL8325
Preliminary
68
"(""<""-'/
All unused, general purpose I/O pins can be tied to V
CC
, GND, or HIZ (high impedance) internally
using the Configuration Editor. This option is given in the bottom-right corner of the placement
window. To use the Placement Editor, choose
Constraint
>
Fix Placement
in the Option pull-
down menu of SpDE.
The rest of the pins should be terminated at the board level in the manner presented in
< 03
.
0431"
<&3&&&&
"%
"<""
PLLOUT<x>
a
a. x represents a number.
b. y represents an aphabetical character.
Unused PLL output pins must be connected to either V
CC
or GND so that their associated
input buffer never floats. Utilized PLL output pins that route the PLL clock outside of the
chip should not be tied to either V
CC
or GND.
IOCTRL<y>
b
There is an internal pulldown resistor to Ground on this pin. This pin should be tied to
Ground if it is not used. For backwards compatibility with Eclipse, it can be tied to Vcc or
Ground. If tied to Vcc, it will draw no more than 20 μA per IOCTRL pin due to the pulldown
resistor.
CLK/PLLIN<x>
Any unused clock pins should be connected to V
CC
or GND.
PLLRST<x>
If a PLL module is not used, then the associated PLLRST<x> must be connected to V
CC
,
under normal operation use it as needed.
INREF<y>
If an I/O bank does not require the use of INREF signal the pin should be connected to
GND.
Eclipse-II
QL8325-7PQ208C
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