參數(shù)資料
型號： PSD413A2V-A-20JI
廠商： 意法半導體
英文描述： Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述： Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁數(shù)： 72/120頁
文件大?。?/td> 563K
代理商： PSD413A2V-A-20JI
PSD813F1-A
Preliminary
68
The
PSD813F1
Functional
Blocks
(cont.)
Access
5V V
CC
,
Typical
Standby
Current
50 μA
(Note 2)
PLD
Memory
Access
Time
Recovery Time
to Normal
Access
Propagation
Delay
Normal tpd
(Note 1)
Mode
Power Down
No Access
tLVDV
Table 30. PSD813F1 Timing and Standby Current During Power
Down Mode
NOTES:
1. Power Down does not affect the operation of the PLD. The PLD operation in this
mode is based only on the Turbo Bit.
2. Typical current consumption assuming no PLD inputs are changing state and
the PLD Turbo bit is off.
Port Function
MCU I/O
PLD Out
Address Out
Data Port
Peripheral I/O
Pin Level
No Change
No Change
Undefined
Three-State
Three-State
Table 29. Power Down Mode’s Effect on
Ports
9.5.1 Automatic Power Down (APD) Unit and Power Down Mode (cont.)
Power Down Mode
By default, if you enable the PSD APD unit, Power Down Mode is automatically enabled.
The device will enter Power Down Mode if the address strobe (ALE/AS) remains inactive for
fifteen CLKIN (pin PD1) clock periods.
The following should be kept in mind when the PSD is in Power Down Mode:
If the address strobe starts pulsing again, the PSD will return to normal operation.
The PSD will also return to normal operation if either the CSI input returns low or the
Reset input returns high.
The MCU address/data bus is blocked from all memories and PLDs.
Various signals can be blocked (prior to Power Down Mode) from entering the PLDs
by setting the appropriate bits in the PMMR registers. The blocked signals include
MCU control signals and the common clock (CLKIN). Note that blocking CLKIN from
the PLDs will not block CLKIN from the APD unit.
All PSD memories enter Standby Mode and are drawing standby current. However,
the PLDs and I/O ports do
not
go into Standby Mode because you don
’
t want to have
to wait for the logic and I/O to
“
wake-up
”
before their outputs can change. See table 29
for Power Down Mode effects on PSD ports.
Typical standby current is 50 μA for 5 V devices, and 25 μA for 3 V devices. These
standby current values assume that there are no transitions on any PLD input.
HC11 (or compatible) Users Note
The HC11 turns off its E clock when it sleeps. Therefore, if you are using an HC11
(or compatible) in your design, and you wish to use the Power Down, you must not
connect the E clock to the CLKIN input (PD1). You should instead connect an
independent clock signal to the CLKIN input. The clock frequency must be
less than
15 times the frequency of AS. The reason for this is that if the frequency is greater than
15 times the frequency of AS, the PSD813F1 will keep going into Power Down Mode.
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