參數(shù)資料
型號: PSD413A2V-A-20JI
廠商: 意法半導體
英文描述: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述: Flash在系統(tǒng)可編程ISP的外設的8位微控制器
文件頁數(shù): 18/120頁
文件大小: 563K
代理商: PSD413A2V-A-20JI
PSD813F1-A
Preliminary
14
Table 7 shows the offset addresses to the PSD813F1 registers relative to the CSIOP base
address. The CSIOP space is the 256 bytes of address that is allocated by the user to the
internal PSD813F1 registers. Table 7 provides brief descriptions of the registers in CSIOP
space. For a more detailed description, refer to section 9.
Table 7. Register Address Offset
8.0
PSD813F1
Register
Description
and Address
Offset
Register Name
Port A Port B Port C Port D Other*
Description
Data In
00
01
10
11
Reads Port pin as input,
MCU I/O input mode
Selects mode between
MCU I/O or Address Out
Stores data for output
to Port pins, MCU I/O
output mode
Configures Port pin as
input or output
Configures Port pins as
either CMOS or Open
Drain on some pins, while
selecting high slew rate
on other pins.
Reads Input Micro
Cells
Reads the status of the
output enable to the I/O
Port driver
Read
reads output of
Micro
Cells AB
Write
loads Micro
cell
Flip-Flops
Read
reads output of
Micro
Cells BC
Write
loads Micro
cell
Flip-Flops
Blocks writing to the
Output Micro
Cells AB
Blocks writing to the
Output Micro
Cells BC
Read only
Flash Sector
Protection
Read only
PSD Security
and EEPROM Sector
Protection
Enables JTAG Port
Power Management
Register 0
Power Management
Register 2
Page Register
Places PSD memory
areas in Program and/or
Data space on an
individual basis.
Control
02
03
Data Out
04
05
12
13
Direction
06
07
14
15
Drive Select
08
09
16
17
Input Micro
Cell
0A
0B
18
Enable Out
0C
0D
1A
1B
Output
Micro
Cells AB
20
20
Output
Micro
Cells BC
21
21
Mask
Micro
Cells AB
Mask
Micro
Cells BC
22
22
23
23
Flash Protection
C0
PSD/EE
Protection
C2
JTAG Enable
C7
PMMR0
B0
PMMR2
B4
Page
E0
VM
E2
*
Other registers that are not part of the I/O ports.
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