參數(shù)資料
型號： PSD413A2V-A-20JI
廠商： 意法半導(dǎo)體
英文描述： Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述： Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁數(shù)： 51/120頁
文件大?。?/td> 563K
代理商： PSD413A2V-A-20JI
Preliminary
PSD813F1-A
47
The
PSD813F1
Functional
Blocks
(cont.)
9.3.3 Data Byte Enable Reference
Microcontrollers have different data byte orientations. The following table shows how the
PSD813F1 interprets byte/word operations in different bus write configurations. Even-byte
refers to locations with address A0 equal to zero and odd byte as locations with A0 equal
to one.
BHE
A0
D7-D0
X
X
0
1
Even Byte
Odd Byte
Table 18. Eight-Bit Data Bus
9.3.4 Microcontroller Interface Examples
Figures 19 through 23 show examples of the basic connections between the PSD813F1
and some popular microcontrollers. The PSD813F1 Control input pins are labeled as to the
microcontroller function for which they are configured. The MCU interface is specified using
the PSDsoft Configuration.
9.3.4.1 80C31
Figure 19 shows the interface to the 80C31, which has an 8-bit multiplexed address/data
bus. The lower address byte is multiplexed with the data bus. The microcontroller control
signals PSEN, RD, and WR may be used for accessing the internal memory components
and I/O Ports. The ALE input (pin PD0) latches the address.
9.3.4.2 80C251
The Intel 80C251 microcontroller features a user-configurable bus interface with four
possible bus configurations, as shown in Table 19.
Configuration 1 is 80C31 compatible, and the bus interface to the PSD813F1 is identical to
that shown in Figure 19. Configurations 2 and 3 have the same bus connection as shown in
Figure 20. There is only one read input (PSEN) connected to the Cntl1 pin on the
PSD813F1. The A16 connection to the PA0 pin allows for a larger address input to the
PSD813F1. Configuration 4 is shown in Figure 21. The RD signal is connected to Cntl1 and
the PSEN signal is connected to the CNTL2.
The 80C251 has two major operating modes: Page Mode and Non-Page Mode. In
Non-Page Mode, the data is multiplexed with the lower address byte, and ALE is active in
every bus cycle. In Page Mode, data D[7:0] is multiplexed with address A[15:8]. In a bus
cycle where there is a Page hit, the ALE signal is not active and only addresses A[7:0]
are changing. The PSD813F1 supports both modes. In Page Mode, the PSD bus timing
is identical to Non-Page Mode except the address hold time and setup time with respect
to ALE is not required. The PSD access time is measured from address A[7:0] valid to
data in valid.
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PSD4235G2-90U 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4235G2-90UI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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