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| 型號(hào)： | PSD413A2V-A-20JI |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| 中文描述： | Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器 |
| 文件頁(yè)數(shù)： | 27/120頁(yè) |
| 文件大?。?/td> | 563K |
| 代理商： | PSD413A2V-A-20JI |
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Preliminary
PSD813F1-A
23
WRITE AAh to
Address 555h
WRITE 55h to
Address AAAh
WRITE A0h to
Address 555h
Page Write
Instruction
SDP is set
WRITE AAh to
Address 555h
WRITE 55h to
Address AAAh
WRITE A0h to
Address 555h
WRITE Data to
be Written in
any Address
Page Write
Instruction
SDP
Set
SDP
not Set
Write
in Memory
Write Data
+
SDP Set
after tWC
(Write Cycle Time)
WRITE
is enabled
SDP ENABLE ALGORITHM
Figure 3. EEPROM SDP Enable Flowcharts
The
PSD813F1
Functional
Blocks
(cont.)
9.1.1.6.3 EEPROM Software Data Protect (SDP)
(cont.)
To enable SDP mode at run time, the MCU must write three specific data bytes at three
specific memory locations, as shown in Figure 3. Any further writes to EEPROM when SDP
is set will require this same sequence, followed by the byte(s) to write. The first SDP enable
sequence can be followed directly by the byte(s) to be written.
To disable SDP mode, the MCU must write specific bytes to six specific locations, as shown
in Figure 4.
The MCU must not be executing code from EEPROM when these instructions are invoked.
The MCU must be operating from some other memory when enabling or disabling SDP
mode.
The state of SDP mode is not changed by power on/off sequences (nonvolatile). When
either the SDP enable or SDP disable instructions are issued from the MCU, the MCU must
use the Toggle bit (status bit DQ6) or the Ready/Busy output pin to check programming
status. The Ready/Busy output is driven low from the first write of AAh @ 555h until the
completion of the internal storage sequence. Data Polling (status bit DQ7) is not supported
when issuing the SDP enable or SDP disable commands.
Note:
Using the SDP sequence (enabling, disabling, or writing data) is initiated when
specific bytes are written to addresses on specific
“
pages
”
of EEPROM memory, with no
more than 120 μsec between writes. The addresses 555h and AAAh are located on
different pages of EEPROM. This is how the PSD813F1 distinguishes these instruction
sequences from ordinary writes to EEPROM, which are expected to be within a single
EEPROM page.
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|---|---|
| PSD4-16 | 制造商:Tamura Corporation of America 功能描述: |
| PSD4-20 | 制造商:MICROTRAN 功能描述:POWER TRANSFORMER, 6 VA |
| PSD4235G2-70U | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD4235G2-90U | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4235G2-90UI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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