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參數(shù)資料
| 型號(hào)： | PSD413A2V-A-20JI |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| 中文描述： | Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器 |
| 文件頁(yè)數(shù)： | 7/120頁(yè) |
| 文件大?。?/td> | 563K |
| 代理商： | PSD413A2V-A-20JI |
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Preliminary
PSD813F1-A
3
J
A simple interface to 8-bit microcontrollers that use either multiplexed or
non-multiplexed busses. The bus interface logic uses the control signals generated by
the microcontroller automatically when the address is decoded and a read or write is
performed. A partial list of the MCU families supported include:
Intel 8031, 80196, 80186, 80C251, and 80386EX
Motorola 68HC11, 68HC16, 68HC12, and 683XX
Philips 8031 and 8051XA
Zilog Z80 and Z8
J
Internal 1 Mbit Flash memory. This is the main Flash memory. It is divided into eight
equal-sized blocks that can be accessed with user-specified addresses.
J
Internal secondary 256 Kbit EEPROM memory. It is divided into four equal-sized blocks
that can be accessed with user-specified addresses. This secondary memory brings
the ability to execute code and update the main Flash
concurrently.
J
16 Kbit scratchpad SRAM. The SRAM’s contents can be protected from a power failure
by connecting an external battery.
J
Optional 64 byte One Time Programmable (OTP) memory that can be used for product
configuration and calibration.
J
CPLD with 16 Output Micro
Cells (OMCs) and 24 Input Micro
Cells (IMCs). The
CPLD may be used to efficiently implement a variety of logic functions for internal
and external control. Examples include state machines, loadable shift registers, and
loadable counters.
J
Decode PLD (DPLD) that decodes address for selection of internal memory blocks.
The DPLD can also be used to generate external chip selects.
J
27 individually configurable I/O port pins that can be used for the following functions:
MCU I/Os
PLD I/Os
Latched MCU address output
Special function I/Os.
16 of the I/O ports may be configured as open-drain outputs.
J
Standby current as low as 50 μA for 5 V devices, 25 μA for 3 V devices.
J
Built-in JTAG compliant serial port allows full-chip In-System Programmability (ISP).
With it, you can program a blank device or reprogram a device in the factory or the field.
J
Internal page register that can be used to expand the microcontroller address space by
a factor of 256.
J
Internal programmable Power Management Unit (PMU) that supports a low power mode
called Power Down Mode. The PMU can automatically detect a lack of microcontroller
activity and put the PSD813F1 into Power Down Mode.
J
Erase/Write cycles:
Flash memory – 100,000 minimum
EEPROM – 10,000 minimum
PLD – 1,000 minimum
Data Retention: 15 year minimum at 90 degrees Celsius (for Main Flash, Boot, PLD
and Configuration bits).
2.0
Key Features
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| PSD4-16 | 制造商:Tamura Corporation of America 功能描述: |
| PSD4-20 | 制造商:MICROTRAN 功能描述:POWER TRANSFORMER, 6 VA |
| PSD4235G2-70U | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD4235G2-90U | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4235G2-90UI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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