- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384854 > PSD413A2V-A-20JI (意法半導(dǎo)體) Flash In-System Programmable ISP Peripherals For 8-bit MCUs PDF資料下載
參數(shù)資料
| 型號： | PSD413A2V-A-20JI |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| 中文描述： | Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器 |
| 文件頁數(shù)： | 43/120頁 |
| 文件大小： | 563K |
| 代理商： | PSD413A2V-A-20JI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁當前第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁
Preliminary
PSD813F1-A
39
9.2.2.2 The Product Term Allocator
The CPLD has a Product Term Allocator. The PSDabel compiler uses the Allocator to
borrow and place product terms from one Micro
Cell to another. The following list
summarizes how product terms are allocated:
McellAB0-7 all have three native product terms and may borrow up to six more
McellBC0-3 all have four native product terms and may borrow up to five more
McellBC4-7 all have four native product terms and may borrow up to six more.
Each Micro
Cell may only borrow product terms from certain other Micro
Cells. Product
terms already in use by one Micro
Cell will not be available for a different Micro
Cell.
If an equation requires more product terms than what is available to it, then
“
external
”
product terms will be required, which will consume other OMCs. If external product terms
are used, extra delay will be added for the equation that required the extra product terms.
This is called product term expansion. PSDsoft will perform this expansion as needed.
9.2.2.3 Loading and Reading the Output Micro
Cells (OMCs)
The OMCs occupy a memory location in the MCU address space, as defined by the
CSIOP (refer to the I/O section). The flip-flops in each of the 16 OMCs can be loaded from
the data bus by a microcontroller. Loading the OMCs with data from the MCU takes priority
over internal functions. As such, the preset, clear, and clock inputs to the flip-flop can be
overridden by the MCU. The ability to load the flip-flops and read them back is useful in
such applications as loadable counters and shift registers, mailboxes, and handshaking
protocols.
Data can be loaded to the OMCs on the trailing edge of the WR signal (edge loading) or
during the time that the WR signal is active (level loading). The method of loading is
specified in PSDsoft Configuration.
9.2.2.4 The OMC Mask Register
There is one Mask Register for each of the two groups of eight OMCs. The Mask Registers
can be used to block the loading of data to individual OMCs. The default value for the Mask
Registers is 00h, which allows loading of the OMCs. When a given bit in a Mask Register is
set to a
‘
1
’
, the MCU will be blocked from writing to the associated OMC. For example,
suppose McellAB0-3 are being used for a state machine. You would not want a MCU write
to McellAB to overwrite the state machine registers. Therefore, you would want to load the
Mask Register for McellAB (Mask Micro
Cell AB) with the value 0Fh.
9.2.2.5 The Output Enable of the OMC
The OMC can be connected to an I/O port pin as a PLD output. The output enable of each
Port pin driver is controlled by a single product term from the AND array, ORed with the
Direction Register output. The pin is enabled upon power up if no output enable equation is
defined and if the pin is declared as a PLD output in PSDsoft.
If the OMC output is declared as an internal node and not as a Port pin output in the
PSDabel file, then the Port pin can be used for other I/O functions. The internal node
feedback can be routed as an input to the AND array.
The
PSD813F1
Functional
Blocks
(cont.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSO-0505 | ECONOLING - DC/DC - CONVERTER |
| PSOT03C | STANDARD CAPACITANCE TVS ARRAY |
| PSOT03LC-LF-T13 | ULTRA LOW CAPACITANCE TVS ARRAY |
| PSOT03LC-LF-T7 | ULTRA LOW CAPACITANCE TVS ARRAY |
| PSOT03LC-T13 | ULTRA LOW CAPACITANCE TVS ARRAY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4-16 | 制造商:Tamura Corporation of America 功能描述: |
| PSD4-20 | 制造商:MICROTRAN 功能描述:POWER TRANSFORMER, 6 VA |
| PSD4235G2-70U | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD4235G2-90U | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4235G2-90UI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。